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Rework xilinx_dsp postAdd for new wreduce call

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This commit is contained in:
Eddie Hung 2019-09-25 17:22:30 -07:00
parent 63940913d2
commit aeb1539818
1 changed files with 3 additions and 3 deletions
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6
passes/pmgen/xilinx_dsp.pmg
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@ -271,9 +271,9 @@ match postAdd
filter !ffMcemux || nusers(port(postAdd, AB)) == 3 filter !ffMcemux || nusers(port(postAdd, AB)) == 3
index <SigBit> port(postAdd, AB)[0] === sigP[0] index <SigBit> port(postAdd, AB)[0] === sigP[0]
filter GetSize(port(postAdd, AB)) <= GetSize(sigP) filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB))) filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1 filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP))
set postAddAB AB set postAddAB AB
optional optional
endmatch endmatch