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Add whitebox support to DRAM

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This commit is contained in:
Eddie Hung 2019-05-23 08:58:57 -07:00
parent 4f44e3399b
commit ae89e6ab26
5 changed files with 26 additions and 24 deletions
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14
techlibs/xilinx/abc.box
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@ -25,3 +25,17 @@ CARRY4 3 1 10 8
- 469 548 528 - 205 558 618 - 469 548 528 - 205 558 618
- - 292 376 - - 226 330 - - 292 376 - - 226 330
- - - 380 - - - 227 - - - 380 - - - 227
# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 4 1 15 2
- - - - - - - 124 124 124 124 124 124 - -
124 124 124 124 124 124 - - - - - - 124 - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 5 1 17 2
- - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - -

10
techlibs/xilinx/cells_sim.v
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@ -281,8 +281,9 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
endmodule endmodule
(* abc_box_id = 4, lib_whitebox *)
module RAM64X1D ( module RAM64X1D (
(* abc_flop_q *) output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,
input A0, A1, A2, A3, A4, A5, input A0, A1, A2, A3, A4, A5,
input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@ -294,12 +295,15 @@ module RAM64X1D (
reg [63:0] mem = INIT; reg [63:0] mem = INIT;
assign SPO = mem[a]; assign SPO = mem[a];
assign DPO = mem[dpra]; assign DPO = mem[dpra];
`ifndef _ABC
wire clk = WCLK ^ IS_WCLK_INVERTED; wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[a] <= D; always @(posedge clk) if (WE) mem[a] <= D;
`endif
endmodule endmodule
(* abc_box_id = 5, lib_whitebox *)
module RAM128X1D ( module RAM128X1D (
(* abc_flop_q *) output DPO, SPO, output DPO, SPO,
input D, WCLK, WE, input D, WCLK, WE,
input [6:0] A, DPRA input [6:0] A, DPRA
); );
@ -308,8 +312,10 @@ module RAM128X1D (
reg [127:0] mem = INIT; reg [127:0] mem = INIT;
assign SPO = mem[A]; assign SPO = mem[A];
assign DPO = mem[DPRA]; assign DPO = mem[DPRA];
`ifndef _ABC
wire clk = WCLK ^ IS_WCLK_INVERTED; wire clk = WCLK ^ IS_WCLK_INVERTED;
always @(posedge clk) if (WE) mem[A] <= D; always @(posedge clk) if (WE) mem[A] <= D;
`endif
endmodule endmodule
module SRL16E ( module SRL16E (

4
techlibs/xilinx/cells_xtra.sh
View file

@ -116,7 +116,7 @@ function xtract_cell_decl()
xtract_cell_decl PS7 "(* keep *)" xtract_cell_decl PS7 "(* keep *)"
xtract_cell_decl PULLDOWN xtract_cell_decl PULLDOWN
xtract_cell_decl PULLUP xtract_cell_decl PULLUP
xtract_cell_decl RAM128X1D #xtract_cell_decl RAM128X1D
xtract_cell_decl RAM128X1S xtract_cell_decl RAM128X1S
xtract_cell_decl RAM256X1S xtract_cell_decl RAM256X1S
xtract_cell_decl RAM32M xtract_cell_decl RAM32M
@ -125,7 +125,7 @@ function xtract_cell_decl()
xtract_cell_decl RAM32X1S_1 xtract_cell_decl RAM32X1S_1
xtract_cell_decl RAM32X2S xtract_cell_decl RAM32X2S
xtract_cell_decl RAM64M xtract_cell_decl RAM64M
xtract_cell_decl RAM64X1D x#tract_cell_decl RAM64X1D
xtract_cell_decl RAM64X1S xtract_cell_decl RAM64X1S
xtract_cell_decl RAM64X1S_1 xtract_cell_decl RAM64X1S_1
xtract_cell_decl RAM64X2S xtract_cell_decl RAM64X2S

18
techlibs/xilinx/cells_xtra.v
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@ -3655,17 +3655,6 @@ module PULLUP (...);
output O; output O;
endmodule endmodule
module RAM128X1D (...);
parameter [127:0] INIT = 128'h00000000000000000000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output DPO, SPO;
input [6:0] A;
input [6:0] DPRA;
input D;
input WCLK;
input WE;
endmodule
module RAM128X1S (...); module RAM128X1S (...);
parameter [127:0] INIT = 128'h00000000000000000000000000000000; parameter [127:0] INIT = 128'h00000000000000000000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0; parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@ -3756,13 +3745,6 @@ module RAM64M (...);
input WE; input WE;
endmodule endmodule
module RAM64X1D (...);
parameter [63:0] INIT = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
output DPO, SPO;
input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
endmodule
module RAM64X1S (...); module RAM64X1S (...);
parameter [63:0] INIT = 64'h0000000000000000; parameter [63:0] INIT = 64'h0000000000000000;
parameter [0:0] IS_WCLK_INVERTED = 1'b0; parameter [0:0] IS_WCLK_INVERTED = 1'b0;

4
techlibs/xilinx/synth_xilinx.cc
View file

@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
{ {
if (check_label("begin")) { if (check_label("begin")) {
if (vpr) if (vpr)
run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else else
run("read_verilog -lib +/xilinx/cells_sim.v"); run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
run("read_verilog -lib +/xilinx/cells_xtra.v"); run("read_verilog -lib +/xilinx/cells_xtra.v");