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Add whitebox support to DRAM

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This commit is contained in:
Eddie Hung 2019-05-23 08:58:57 -07:00
parent 4f44e3399b
commit ae89e6ab26
5 changed files with 26 additions and 24 deletions
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4
techlibs/xilinx/synth_xilinx.cc
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@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
{
if (check_label("begin")) {
if (vpr)
run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
else
run("read_verilog -lib +/xilinx/cells_sim.v");
run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
run("read_verilog -lib +/xilinx/cells_xtra.v");