diff --git a/tests/opt/opt_merge_basic.ys b/tests/opt/opt_merge_basic.ys
index e6336f648..082fdb0b8 100644
--- a/tests/opt/opt_merge_basic.ys
+++ b/tests/opt/opt_merge_basic.ys
@@ -1,13 +1,74 @@
-read_verilog -icells <<EOT
+read_verilog <<EOT
 module top(A, B, X, Y);
-input [8:0] A, B;
-output [8:0] X, Y;
+input [7:0] A, B;
+output [7:0] X, Y;
 assign X = A + B;
 assign Y = A + B;
 endmodule
 EOT
-
+# Most basic case
+# Binary
 select -assert-count 2 t:$add
 equiv_opt -assert opt_merge
 design -load postopt
 select -assert-count 1 t:$add
+
+design -reset
+read_verilog <<EOT
+module top(A, B, C, X, Y);
+input [7:0] A, B, C;
+output [7:0] X, Y;
+assign X = A + B;
+assign Y = A + C;
+endmodule
+EOT
+# Reject on a different input
+select -assert-count 2 t:$add
+opt_merge
+select -assert-count 2 t:$add
+
+design -reset
+read_verilog <<EOT
+module top(A, X, Y);
+input [7:0] A;
+output X, Y;
+assign X = ^A;
+assign Y = ^A;
+endmodule
+EOT
+# Unary
+select -assert-count 2 t:$reduce_xor
+dump
+opt_merge
+select -assert-count 1 t:$reduce_xor
+
+design -reset
+read_verilog -icells <<EOT
+module top(A, B, X, Y);
+input [7:0] A;
+input [7:0] B;
+output X, Y;
+  \$reduce_or  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd16),
+    .Y_WIDTH(32'd1),
+  ) one  (
+    .A({A, B}), // <- look here
+    .Y(X)
+  );
+  \$reduce_or  #(
+    .A_SIGNED(32'd0),
+    .A_WIDTH(32'd16),
+    .Y_WIDTH(32'd1),
+  ) other  (
+    .A({B, A}), // <- look here
+    .Y(Y)
+  );
+endmodule
+EOT
+# Unary
+opt_expr
+select -assert-count 2 t:$reduce_or
+equiv_opt -assert opt_merge
+design -load postopt
+select -assert-count 1 t:$reduce_or