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Fixed xilinx/example_sim_counter test bench

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This commit is contained in:
Clifford Wolf 2013-11-24 17:55:46 +01:00
parent 41205afc39
commit ae798d3fd5
1 changed files with 1 additions and 1 deletions
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techlibs/xilinx/example_sim_counter/run_sim.sh
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@ -8,7 +8,7 @@ XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
iverilog -o testbench_gold counter_tb.v counter.v
iverilog -o testbench_gate counter_tb.v testbench_synth.v \
$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v
./testbench_gold > testbench_gold.txt
./testbench_gate > testbench_gate.txt