From f90b965d990afd4c85ada76d7d164daaa01c9ea1 Mon Sep 17 00:00:00 2001 From: Stan Lee Date: Tue, 7 Jul 2026 09:43:43 -0700 Subject: [PATCH 1/5] add runtime flag for verific frontend --- frontends/verific/verific.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index ce5760a4e..c197ec1b1 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3774,6 +3774,9 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); // RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); // SILIMATE: control this externally // RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); // SILIMATE: control this externally + // SILIMATE: per-signal RAM extraction opt-in, comma-separated . entries + RuntimeFlags::AddStringVar("veri_force_ram_signals", nullptr, + "Each matching signal behaves as if it had a (* force_ram *) attribute in the RTL."); RuntimeFlags::SetVar("veri_replace_const_exprs", 1); #endif #ifdef VERIFIC_VHDL_SUPPORT From 0027cc4a4e010800787161112f46856eb816575d Mon Sep 17 00:00:00 2001 From: Stan Lee Date: Tue, 7 Jul 2026 10:10:33 -0700 Subject: [PATCH 2/5] register -force-ram in verific frontend --- frontends/verific/verific.cc | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c197ec1b1..085e62f5d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3513,6 +3513,13 @@ struct VerificPass : public Pass { log("Remove Verilog defines previously set with -vlog-define.\n"); log("\n"); log("\n"); + log(" verific -force-ram ...\n"); + log("\n"); + log("Treat each listed signal as if it had a (* force_ram *) attribute in the\n"); + log("RTL, opting it into multi-port RAM extraction. Must be used before the\n"); + log("Verilog sources are analyzed.\n"); + log("\n"); + log("\n"); #endif log(" verific -set-error ..\n"); log(" verific -set-warning ..\n"); @@ -3774,9 +3781,6 @@ struct VerificPass : public Pass { RuntimeFlags::SetVar("veri_extract_dualport_rams", 0); // RuntimeFlags::SetVar("veri_extract_multiport_rams", 1); // SILIMATE: control this externally // RuntimeFlags::SetVar("veri_allow_any_ram_in_loop", 1); // SILIMATE: control this externally - // SILIMATE: per-signal RAM extraction opt-in, comma-separated . entries - RuntimeFlags::AddStringVar("veri_force_ram_signals", nullptr, - "Each matching signal behaves as if it had a (* force_ram *) attribute in the RTL."); RuntimeFlags::SetVar("veri_replace_const_exprs", 1); #endif #ifdef VERIFIC_VHDL_SUPPORT @@ -3927,6 +3931,13 @@ struct VerificPass : public Pass { goto check_error; } + // SILIMATE: register signals that behave as if annotated with (* force_ram *) in the RTL + if (GetSize(args) > argidx && args[argidx] == "-force-ram") { + for (argidx++; argidx < GetSize(args); argidx++) + veri_file::AddForceRamSignal(args[argidx].c_str()); + goto check_error; + } + veri_file::RemoveAllLOptions(); #endif for (int i = argidx; i < GetSize(args); i++) From b146da984f5e47e0652269b45c4a686db5e8b43f Mon Sep 17 00:00:00 2001 From: Stan Lee Date: Tue, 7 Jul 2026 13:25:50 -0700 Subject: [PATCH 3/5] implementation that works without verific changes --- frontends/verific/verific.cc | 47 +++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 085e62f5d..f8de10d38 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -58,6 +58,8 @@ USING_YOSYS_NAMESPACE #include "VeriWrite.h" #include "VeriLibrary.h" #include "VeriExpression.h" +#include "VeriScope.h" +#include "VeriId.h" #endif #ifdef VERIFIC_VHDL_SUPPORT @@ -121,6 +123,37 @@ bool verific_no_split_complex_ports; // SILIMATE: disable splitting of complex p #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT vector verific_incdirs, verific_libdirs, verific_libexts; +// SILIMATE: "." entries to treat as if annotated with (* force_ram *) +vector verific_force_ram_signals; + +// SILIMATE: stamp the force_ram attribute onto the registered signals. +static void apply_force_ram_signals() +{ + for (auto &entry : verific_force_ram_signals) { + // Validation + size_t dot = entry.find('.'); + if (dot == std::string::npos || dot == 0 || dot + 1 == entry.size()) { + log_warning("-force-ram entry '%s' is not of the form . required.\n", entry.c_str()); + continue; + } + // Extract module and signal name + std::string module_name = entry.substr(0, dot); + std::string signal_name = entry.substr(dot + 1); + // Find module and signal from the design + VeriModule *veri_module = veri_file::GetModule(module_name.c_str()); + VeriScope *scope = veri_module ? veri_module->GetScope() : nullptr; + VeriIdDef *id = scope ? scope->FindLocal(signal_name.c_str()) : nullptr; + if (!id) { + log_warning("-force-ram: signal '%s' not found in module '%s'.\n", + signal_name.c_str(), module_name.c_str()); + continue; + } + // Add force_ram attribute if not already present + if (!id->GetAttribute("force_ram")) + id->AddAttribute("force_ram", nullptr); + } +} + static void dump_verific_file_closure(const char *output_path, Array *file_names) { std::set seen; @@ -3030,6 +3063,9 @@ void restore_blackbox_msg_state() void import_all(const char* work, std::map *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED) { +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + apply_force_ram_signals(); // SILIMATE +#endif #ifdef YOSYSHQ_VERIFIC_EXTENSIONS save_blackbox_msg_state(); VerificExtensions::ElaborateAndRewrite(work, parameters); @@ -3099,6 +3135,10 @@ std::set import_tops(const char* work, std::map...\n"); log("\n"); log("Treat each listed signal as if it had a (* force_ram *) attribute in the\n"); - log("RTL, opting it into multi-port RAM extraction. Must be used before the\n"); - log("Verilog sources are analyzed.\n"); + log("RTL, opting it into multi-port RAM extraction. The attribute is applied\n"); + log("when the design is elaborated (verific -import).\n"); log("\n"); log("\n"); #endif @@ -3934,7 +3975,7 @@ struct VerificPass : public Pass { // SILIMATE: register signals that behave as if annotated with (* force_ram *) in the RTL if (GetSize(args) > argidx && args[argidx] == "-force-ram") { for (argidx++; argidx < GetSize(args); argidx++) - veri_file::AddForceRamSignal(args[argidx].c_str()); + verific_force_ram_signals.push_back(args[argidx]); goto check_error; } From 3a1f4e00cace137717487effc151345e4f185e45 Mon Sep 17 00:00:00 2001 From: Stan Lee Date: Tue, 7 Jul 2026 14:48:21 -0700 Subject: [PATCH 4/5] log forced --- frontends/verific/verific.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f8de10d38..e19eb719b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -149,8 +149,11 @@ static void apply_force_ram_signals() continue; } // Add force_ram attribute if not already present - if (!id->GetAttribute("force_ram")) + if (!id->GetAttribute("force_ram")) { id->AddAttribute("force_ram", nullptr); + log("Added force_ram attribute to signal '%s' in module '%s'.\n", + signal_name.c_str(), module_name.c_str()); + } } } From 0e906c1d3e96a00dcd04e07fcdaf982359282762 Mon Sep 17 00:00:00 2001 From: Stan Lee Date: Tue, 7 Jul 2026 15:40:07 -0700 Subject: [PATCH 5/5] address greptile --- frontends/verific/verific.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index e19eb719b..24e4bb19d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -127,7 +127,7 @@ vector verific_incdirs, verific_libdirs, verific_libexts; vector verific_force_ram_signals; // SILIMATE: stamp the force_ram attribute onto the registered signals. -static void apply_force_ram_signals() +static void apply_force_ram_signals(const char *work) { for (auto &entry : verific_force_ram_signals) { // Validation @@ -140,7 +140,11 @@ static void apply_force_ram_signals() std::string module_name = entry.substr(0, dot); std::string signal_name = entry.substr(dot + 1); // Find module and signal from the design - VeriModule *veri_module = veri_file::GetModule(module_name.c_str()); + VeriModule *veri_module = veri_file::GetModule(module_name.c_str(), 1, work); + if (!veri_module) { + log_warning("-force-ram: module '%s' not found.\n", module_name.c_str()); + continue; + } VeriScope *scope = veri_module ? veri_module->GetScope() : nullptr; VeriIdDef *id = scope ? scope->FindLocal(signal_name.c_str()) : nullptr; if (!id) { @@ -3067,7 +3071,7 @@ void restore_blackbox_msg_state() void import_all(const char* work, std::map *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED) { #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - apply_force_ram_signals(); // SILIMATE + apply_force_ram_signals(work); // SILIMATE #endif #ifdef YOSYSHQ_VERIFIC_EXTENSIONS save_blackbox_msg_state(); @@ -3139,7 +3143,7 @@ std::set import_tops(const char* work, std::map