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https://github.com/YosysHQ/yosys
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Fixed opt_clean handling of inout ports
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parent
b659ffb457
commit
ae09c89f62
1 changed files with 2 additions and 2 deletions
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@ -90,7 +90,7 @@ void rmunused_module_cells(Module *module, bool verbose)
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for (auto &it : module->cells_) {
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for (auto &it : module->cells_) {
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Cell *cell = it.second;
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Cell *cell = it.second;
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for (auto &it2 : cell->connections()) {
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for (auto &it2 : cell->connections()) {
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if (!ct_all.cell_input(cell->type, it2.first))
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if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first))
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for (auto bit : sigmap(it2.second))
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for (auto bit : sigmap(it2.second))
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if (bit.wire != nullptr)
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if (bit.wire != nullptr)
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wire2driver[bit].insert(cell);
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wire2driver[bit].insert(cell);
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@ -115,7 +115,7 @@ void rmunused_module_cells(Module *module, bool verbose)
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pool<SigBit> bits;
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pool<SigBit> bits;
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for (auto cell : queue)
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for (auto cell : queue)
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for (auto &it : cell->connections())
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for (auto &it : cell->connections())
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if (!ct_all.cell_output(cell->type, it.first))
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if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it.first))
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for (auto bit : sigmap(it.second))
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for (auto bit : sigmap(it.second))
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bits.insert(bit);
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bits.insert(bit);
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