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Make modtools use SigSpecConstIterator instead of SigSpec::operator[] const
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parent
44fd135b01
commit
adf34bb08e
1 changed files with 12 additions and 7 deletions
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@ -83,19 +83,23 @@ struct ModIndex : public RTLIL::Monitor
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void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
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{
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for (int i = 0; i < GetSize(sig); i++) {
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RTLIL::SigBit bit = sigmap(sig[i]);
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int i = 0;
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for (auto &sig_bit : sig) {
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RTLIL::SigBit bit = sigmap(sig_bit);
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if (bit.wire)
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database[bit].ports.insert(PortInfo(cell, port, i));
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++i;
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}
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}
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void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
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{
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for (int i = 0; i < GetSize(sig); i++) {
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RTLIL::SigBit bit = sigmap(sig[i]);
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int i = 0;
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for (auto &sig_bit : sig) {
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RTLIL::SigBit bit = sigmap(sig_bit);
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if (bit.wire)
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database[bit].ports.erase(PortInfo(cell, port, i));
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++i;
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}
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}
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@ -179,10 +183,11 @@ struct ModIndex : public RTLIL::Monitor
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if (auto_reload_module)
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return;
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for (int i = 0; i < GetSize(sigsig.first); i++)
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RTLIL::SigSpecConstIterator second_it = sigsig.second.begin();
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for (auto &first_bit : sigsig.first)
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{
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RTLIL::SigBit lhs = sigmap(sigsig.first[i]);
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RTLIL::SigBit rhs = sigmap(sigsig.second[i]);
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RTLIL::SigBit lhs = sigmap(first_bit);
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RTLIL::SigBit rhs = sigmap(*second_it++);
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bool has_lhs = database.count(lhs) != 0;
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bool has_rhs = database.count(rhs) != 0;
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