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https://github.com/YosysHQ/yosys
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Added smtc "final" statement
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parent
7500b403de
commit
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5 changed files with 86 additions and 9 deletions
3
examples/smtbmc/.gitignore
vendored
3
examples/smtbmc/.gitignore
vendored
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@ -10,3 +10,6 @@ demo2_tb.vcd
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demo3.smt2
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demo3.vcd
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demo3.yslog
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demo4.smt2
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demo4.vcd
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demo4.yslog
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@ -1,5 +1,5 @@
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all: demo1 demo2 demo3
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all: demo1 demo2 demo3 demo4
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demo1: demo1.smt2
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yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2
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@ -13,6 +13,9 @@ demo2: demo2.smt2
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demo3: demo3.smt2
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yosys-smtbmc --dump-vcd demo3.vcd --smtc demo3.smtc demo3.smt2
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demo4: demo4.smt2
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yosys-smtbmc -s yices --dump-vcd demo4.vcd --smtc demo4.smtc demo4.smt2
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demo1.smt2: demo1.v
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yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires -mem -bv demo1.smt2'
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@ -22,10 +25,14 @@ demo2.smt2: demo2.v
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demo3.smt2: demo3.v
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yosys -ql demo3.yslog -p 'read_verilog -formal demo3.v; prep -top demo3 -nordff; write_smt2 -wires -mem -bv demo3.smt2'
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demo4.smt2: demo4.v
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yosys -ql demo4.yslog -p 'read_verilog -formal demo4.v; prep -top demo4 -nordff; write_smt2 -wires -mem -bv demo4.smt2'
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clean:
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rm -f demo1.yslog demo1.smt2 demo1.vcd
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rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd
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rm -f demo3.yslog demo3.smt2 demo3.vcd
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rm -f demo4.yslog demo4.smt2 demo4.vcd
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.PHONY: demo1 demo2 demo3 clean
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.PHONY: demo1 demo2 demo3 demo4 clean
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11
examples/smtbmc/demo4.smtc
Normal file
11
examples/smtbmc/demo4.smtc
Normal file
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@ -0,0 +1,11 @@
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initial
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assume [rst]
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always -1
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assume (not [rst])
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assume (=> [-1:inv2] [inv2])
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final -2
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assume [-1:inv2]
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assume (not [-2:inv2])
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assert (= [r1] [r2])
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13
examples/smtbmc/demo4.v
Normal file
13
examples/smtbmc/demo4.v
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@ -0,0 +1,13 @@
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// Demo for "final" smtc constraints
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module demo4(input clk, rst, inv2, input [15:0] in, output reg [15:0] r1, r2);
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always @(posedge clk) begin
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if (rst) begin
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r1 <= in;
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r2 <= -in;
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end else begin
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r1 <= r1 + in;
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r2 <= inv2 ? -(r2 - in) : (r2 - in);
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end
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end
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endmodule
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