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https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
Fix top-connectivity and connections to constants
This commit is contained in:
Alain Dargelas
parent
c3bcd0b643
commit
adbf596a7a
1 changed files with 93 additions and 60 deletions
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@ -14,17 +14,41 @@ struct ReconstructBusses : public ScriptPass {
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bool is_digits(const std::string &str) { return std::all_of(str.begin(), str.end(), ::isdigit); }
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// Get the index <index> from the signal name "prefix_<index>_"
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int getIndex(std::string name, std::map<std::string, RTLIL::Wire *> &wirenames_to_remove)
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{
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std::map<std::string, RTLIL::Wire *>::iterator itr_lhs = wirenames_to_remove.find(name);
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if (itr_lhs != wirenames_to_remove.end()) {
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std::string::iterator conn_lhs_end = name.end() - 1;
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if ((*conn_lhs_end) == '_') {
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name = name.substr(0, name.size() - 1);
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if (name.find("_") != std::string::npos) {
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std::string ch_index_str = name.substr(name.find_last_of('_') + 1);
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if (!ch_index_str.empty() && is_digits(ch_index_str)) {
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int ch_index = std::stoi(ch_index_str);
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return ch_index;
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}
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}
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}
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}
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return -1;
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}
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void execute(std::vector<std::string>, RTLIL::Design *design) override
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{
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if (design == nullptr) {
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log_error("No design object");
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return;
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}
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bool debug = false;
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if (std::getenv("DEBUG_RECONSTRUCT_BUSSES")) {
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debug = true;
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}
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log("Running reconstructbusses pass\n");
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log_flush();
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log("Creating bus groups\n");
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log_flush();
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for (auto module : design->modules()) {
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log("Creating bus groups for module %s\n", module->name.str().c_str());
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log_flush();
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// Collect all wires with a common prefix
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dict<std::string, std::vector<RTLIL::Wire *>> wire_groups;
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for (auto wire : module->wires()) {
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@ -83,6 +107,8 @@ struct ReconstructBusses : public ScriptPass {
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// Reconstruct vectors
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for (auto &it : wire_groups) {
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std::string prefix = it.first;
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if (debug)
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std::cout << "Wire group:" << prefix << std::endl;
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std::vector<RTLIL::Wire *> &wires = it.second;
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// Create a new vector wire
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@ -107,39 +133,34 @@ struct ReconstructBusses : public ScriptPass {
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log_flush();
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// Reconnect cells
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for (auto cell : module->cells()) {
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if (debug)
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std::cout << "Cell:" << cell->name.c_str() << std::endl;
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for (auto &conn : cell->connections_) {
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RTLIL::SigSpec new_sig;
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bool modified = false;
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for (auto chunk : conn.second.chunks()) {
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// std::cout << "Port:" << conn.first.c_str() << std::endl;
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// std::cout << "Conn:" << chunk.wire->name.c_str() << std::endl;
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if (debug) {
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std::cout << " Port:" << conn.first.c_str() << std::endl;
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std::cout << " Conn:" << (chunk.wire ? chunk.wire->name.c_str() : "constant") << std::endl;
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}
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// Find the connections that match the wire group prefix
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std::string lhs_name = chunk.wire->name.c_str();
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std::map<std::string, RTLIL::Wire *>::iterator itr = wirenames_to_remove.find(lhs_name);
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if (itr != wirenames_to_remove.end()) {
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std::string ch_name = chunk.wire->name.c_str();
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if (!ch_name.empty()) {
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std::string::iterator ch_end = ch_name.end() - 1;
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if ((*ch_end) == '_') {
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ch_name = ch_name.substr(0, ch_name.size() - 1);
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if (ch_name.find("_") != std::string::npos) {
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std::string ch_index_str =
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ch_name.substr(ch_name.find_last_of('_') + 1);
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// std::cout << "ch_name: " << ch_name << std::endl;
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if ((!ch_index_str.empty() && is_digits(ch_index_str))) {
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// Create a new connection sigspec that matches the previous
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// bit index
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int ch_index = std::stoi(ch_index_str);
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RTLIL::SigSpec bit = RTLIL::SigSpec(itr->second, ch_index, 1);
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new_sig.append(bit);
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modified = true;
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}
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}
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}
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if (chunk.wire == nullptr) {
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continue;
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}
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std::string lhs_name = chunk.wire ? chunk.wire->name.c_str() : "";
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int lhsIndex = getIndex(lhs_name, wirenames_to_remove);
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std::map<std::string, RTLIL::Wire *>::iterator itr_lhs = wirenames_to_remove.find(lhs_name);
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if (itr_lhs != wirenames_to_remove.end()) {
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if (lhsIndex >= 0) {
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// Create a new connection sigspec that matches the previous
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// bit index
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RTLIL::SigSpec bit = RTLIL::SigSpec(itr_lhs->second, lhsIndex, 1);
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new_sig.append(bit);
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modified = true;
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} else {
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new_sig.append(chunk);
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modified = true;
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}
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} else {
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new_sig.append(chunk);
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modified = true;
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}
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}
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// Replace the previous connection
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@ -147,10 +168,17 @@ struct ReconstructBusses : public ScriptPass {
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conn.second = new_sig;
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}
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}
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if (debug)
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run_pass("write_rtlil post_reconnect_cells.rtlil");
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log("Reconnecting top connections\n");
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log_flush();
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// Reconnect top connections before removing the old wires
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std::vector<RTLIL::SigSig> newConnections;
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for (auto &conn : module->connections()) {
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// Keep all the connections that won't get rewired
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newConnections.push_back(conn);
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}
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for (auto &conn : newConnections) {
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RTLIL::SigSpec lhs = conn.first;
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RTLIL::SigSpec rhs = conn.second;
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auto lit = lhs.chunks().rbegin();
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@ -162,40 +190,40 @@ struct ReconstructBusses : public ScriptPass {
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RTLIL::SigChunk sub_rhs = *rit;
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while (lit != lhs.chunks().rend()) {
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RTLIL::SigChunk sub_lhs = *lit;
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std::string conn_lhs = sub_lhs.wire->name.c_str();
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if (!conn_lhs.empty()) {
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// std::cout << "Conn LHS: " << conn_lhs << std::endl;
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// std::string conn_rhs = sub_rhs.wire->name.c_str();
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// std::cout << "Conn RHS: " << conn_rhs << std::endl;
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std::map<std::string, RTLIL::Wire *>::iterator itr = wirenames_to_remove.find(conn_lhs);
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if (itr != wirenames_to_remove.end()) {
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std::string::iterator conn_lhs_end = conn_lhs.end() - 1;
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if ((*conn_lhs_end) == '_') {
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conn_lhs = conn_lhs.substr(0, conn_lhs.size() - 1);
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if (conn_lhs.find("_") != std::string::npos) {
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std::string ch_index_str = conn_lhs.substr(conn_lhs.find_last_of('_') + 1);
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if (!ch_index_str.empty() && is_digits(ch_index_str)) {
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int ch_index = std::stoi(ch_index_str);
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// Create the LHS sigspec of the desired bit
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RTLIL::SigSpec bit = RTLIL::SigSpec(itr->second, ch_index, 1);
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if (sub_rhs.size() > 1) {
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// If RHS has width > 1, replace with the bitblasted RHS
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// corresponding to the connected bit
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RTLIL::SigSpec rhs_bit =
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RTLIL::SigSpec(sub_rhs.wire, ch_index, 1);
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// And connect it
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module->connect(bit, rhs_bit);
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} else {
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// Else, directly connect
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module->connect(bit, sub_rhs);
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}
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std::string conn_lhs_s = sub_lhs.wire ? sub_lhs.wire->name.c_str() : "";
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std::string conn_rhs_s = sub_rhs.wire ? sub_rhs.wire->name.c_str() : "";
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if (!conn_lhs_s.empty()) {
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if (debug) {
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std::cout << "Conn LHS: " << conn_lhs_s << std::endl;
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std::cout << "Conn RHS: " << conn_rhs_s << std::endl;
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}
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int lhsIndex = getIndex(conn_lhs_s, wirenames_to_remove);
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int rhsIndex = getIndex(conn_rhs_s, wirenames_to_remove);
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std::map<std::string, RTLIL::Wire *>::iterator itr_lhs = wirenames_to_remove.find(conn_lhs_s);
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std::map<std::string, RTLIL::Wire *>::iterator itr_rhs = wirenames_to_remove.find(conn_rhs_s);
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if (itr_lhs != wirenames_to_remove.end() || itr_rhs != wirenames_to_remove.end()) {
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if (lhsIndex >= 0) {
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// Create the LHS sigspec of the desired bit
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RTLIL::SigSpec lbit = RTLIL::SigSpec(itr_lhs->second, lhsIndex, 1);
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if (sub_rhs.size() > 1) {
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// If RHS has width > 1, replace with the bitblasted RHS
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// corresponding to the connected bit
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RTLIL::SigSpec rhs_bit = RTLIL::SigSpec(sub_rhs.wire, lhsIndex, 1);
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// And connect it
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module->connect(lbit, rhs_bit);
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} else {
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// Else, directly connect
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if (rhsIndex >= 0) {
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RTLIL::SigSpec rbit = RTLIL::SigSpec(itr_rhs->second, rhsIndex, 1);
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module->connect(lbit, rbit);
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} else {
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// Else, directly connect
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RTLIL::SigSpec bit = RTLIL::SigSpec(itr->second, 0, 1);
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module->connect(bit, sub_rhs);
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module->connect(lbit, sub_rhs);
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}
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}
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} else {
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// Else, directly connect
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RTLIL::SigSpec bit = RTLIL::SigSpec(itr_lhs->second, 0, 1);
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module->connect(bit, sub_rhs);
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}
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}
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}
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@ -204,7 +232,10 @@ struct ReconstructBusses : public ScriptPass {
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rit++;
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}
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}
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if (debug)
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run_pass("write_rtlil post_reconnect_top.rtlil");
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// Remove old wires
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// Cleans the dangling connections too
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log("Removing old wires\n");
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log_flush();
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module->remove(wires_to_remove);
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@ -213,6 +244,8 @@ struct ReconstructBusses : public ScriptPass {
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log_flush();
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module->fixup_ports();
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}
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if (debug)
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run_pass("write_rtlil post_reconstructbusses.rtlil");
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log("End reconstructbusses pass\n");
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log_flush();
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}
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