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Also cope with duplicated CIs

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This commit is contained in:
Eddie Hung 2019-04-12 16:17:12 -07:00
parent c748391730
commit ada130b459
1 changed files with 23 additions and 5 deletions
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28
frontends/aiger/aigerparse.cc
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@ -446,12 +446,30 @@ next_line:
log_assert(wire); log_assert(wire);
log_assert(wire->port_input); log_assert(wire->port_input);
if (index == 0) if (index == 0) {
module->rename(wire, escaped_symbol); // Cope with the fact that a CI might be identical
// to a PI (necessary due to ABC); in those cases
// simply connect the latter to the former
RTLIL::Wire* existing = module->wire(escaped_symbol);
if (!existing)
module->rename(wire, escaped_symbol);
else {
wire->port_input = false;
module->connect(wire, existing);
}
}
else if (index > 0) { else if (index > 0) {
module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); std::string indexed_name = stringf("%s[%d]", escaped_symbol.c_str(), index);
if (wideports) RTLIL::Wire* existing = module->wire(indexed_name);
wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); if (!existing) {
module->rename(wire, indexed_name);
if (wideports)
wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index);
}
else {
module->connect(wire, existing);
wire->port_input = false;
}
} }
} }
else if (type == "output") { else if (type == "output") {