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Fixed CRLF line endings

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Clifford Wolf 2015-08-13 09:35:00 +02:00
parent 08ad5409a2
commit ad8efeb13f
6 changed files with 563 additions and 563 deletions
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246
tests/asicworld/code_hdl_models_arbiter.v
View file

@ -1,123 +1,123 @@
//----------------------------------------------------
// A four level, round-robin arbiter. This was
// orginally coded by WD Peterson in VHDL.
//----------------------------------------------------
module arbiter (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
// --------------Port Declaration-----------------------
input clk;
input rst;
input req3;
input req2;
input req1;
input req0;
output gnt3;
output gnt2;
output gnt1;
output gnt0;
//--------------Internal Registers----------------------
wire [1:0] gnt ;
wire comreq ;
wire beg ;
wire [1:0] lgnt ;
wire lcomreq ;
reg lgnt0 ;
reg lgnt1 ;
reg lgnt2 ;
reg lgnt3 ;
reg lasmask ;
reg lmask0 ;
reg lmask1 ;
reg ledge ;
//--------------Code Starts Here-----------------------
always @ (posedge clk)
if (rst) begin
lgnt0 <= 0;
lgnt1 <= 0;
lgnt2 <= 0;
lgnt3 <= 0;
end else begin
lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
| (~lcomreq & lmask1 & lmask0 & req0 )
| ( lcomreq & lgnt0 );
lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
| ( lcomreq & lgnt1);
lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req2)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
| ( lcomreq & lgnt2);
lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
| (~lcomreq & lmask1 & ~lmask0 & req3)
| (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
| ( lcomreq & lgnt3);
end
//----------------------------------------------------
// lasmask state machine.
//----------------------------------------------------
assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
always @ (posedge clk)
begin
lasmask <= (beg & ~ledge & ~lasmask);
ledge <= (beg & ~ledge & lasmask)
| (beg & ledge & ~lasmask);
end
//----------------------------------------------------
// comreq logic.
//----------------------------------------------------
assign lcomreq = ( req3 & lgnt3 )
| ( req2 & lgnt2 )
| ( req1 & lgnt1 )
| ( req0 & lgnt0 );
//----------------------------------------------------
// Encoder logic.
//----------------------------------------------------
assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
//----------------------------------------------------
// lmask register.
//----------------------------------------------------
always @ (posedge clk )
if( rst ) begin
lmask1 <= 0;
lmask0 <= 0;
end else if(lasmask) begin
lmask1 <= lgnt[1];
lmask0 <= lgnt[0];
end else begin
lmask1 <= lmask1;
lmask0 <= lmask0;
end
assign comreq = lcomreq;
assign gnt = lgnt;
//----------------------------------------------------
// Drive the outputs
//----------------------------------------------------
assign gnt3 = lgnt3;
assign gnt2 = lgnt2;
assign gnt1 = lgnt1;
assign gnt0 = lgnt0;
endmodule
//----------------------------------------------------
// A four level, round-robin arbiter. This was
// orginally coded by WD Peterson in VHDL.
//----------------------------------------------------
module arbiter (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
// --------------Port Declaration-----------------------
input clk;
input rst;
input req3;
input req2;
input req1;
input req0;
output gnt3;
output gnt2;
output gnt1;
output gnt0;
//--------------Internal Registers----------------------
wire [1:0] gnt ;
wire comreq ;
wire beg ;
wire [1:0] lgnt ;
wire lcomreq ;
reg lgnt0 ;
reg lgnt1 ;
reg lgnt2 ;
reg lgnt3 ;
reg lasmask ;
reg lmask0 ;
reg lmask1 ;
reg ledge ;
//--------------Code Starts Here-----------------------
always @ (posedge clk)
if (rst) begin
lgnt0 <= 0;
lgnt1 <= 0;
lgnt2 <= 0;
lgnt3 <= 0;
end else begin
lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
| (~lcomreq & lmask1 & lmask0 & req0 )
| ( lcomreq & lgnt0 );
lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
| ( lcomreq & lgnt1);
lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req2)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
| ( lcomreq & lgnt2);
lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
| (~lcomreq & lmask1 & ~lmask0 & req3)
| (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
| ( lcomreq & lgnt3);
end
//----------------------------------------------------
// lasmask state machine.
//----------------------------------------------------
assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
always @ (posedge clk)
begin
lasmask <= (beg & ~ledge & ~lasmask);
ledge <= (beg & ~ledge & lasmask)
| (beg & ledge & ~lasmask);
end
//----------------------------------------------------
// comreq logic.
//----------------------------------------------------
assign lcomreq = ( req3 & lgnt3 )
| ( req2 & lgnt2 )
| ( req1 & lgnt1 )
| ( req0 & lgnt0 );
//----------------------------------------------------
// Encoder logic.
//----------------------------------------------------
assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
//----------------------------------------------------
// lmask register.
//----------------------------------------------------
always @ (posedge clk )
if( rst ) begin
lmask1 <= 0;
lmask0 <= 0;
end else if(lasmask) begin
lmask1 <= lgnt[1];
lmask0 <= lgnt[0];
end else begin
lmask1 <= lmask1;
lmask0 <= lmask0;
end
assign comreq = lcomreq;
assign gnt = lgnt;
//----------------------------------------------------
// Drive the outputs
//----------------------------------------------------
assign gnt3 = lgnt3;
assign gnt2 = lgnt2;
assign gnt1 = lgnt1;
assign gnt0 = lgnt0;
endmodule

22
tests/asicworld/code_hdl_models_t_gate_switch.v
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@ -1,11 +1,11 @@
module t_gate_switch (L,R,nC,C);
inout L;
inout R;
input nC;
input C;
//Syntax: keyword unique_name (drain. source, gate);
pmos p1 (L,R,nC);
nmos p2 (L,R,C);
endmodule
module t_gate_switch (L,R,nC,C);
inout L;
inout R;
input nC;
input C;
//Syntax: keyword unique_name (drain. source, gate);
pmos p1 (L,R,nC);
nmos p2 (L,R,C);
endmodule

38
tests/asicworld/code_verilog_tutorial_counter.v
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@ -1,19 +1,19 @@
//-----------------------------------------------------
// Design Name : counter
// File Name : counter.v
// Function : 4 bit up counter
// Coder : Deepak
//-----------------------------------------------------
module counter (clk, reset, enable, count);
input clk, reset, enable;
output [3:0] count;
reg [3:0] count;
always @ (posedge clk)
if (reset == 1'b1) begin
count <= 0;
end else if ( enable == 1'b1) begin
count <= count + 1;
end
endmodule
//-----------------------------------------------------
// Design Name : counter
// File Name : counter.v
// Function : 4 bit up counter
// Coder : Deepak
//-----------------------------------------------------
module counter (clk, reset, enable, count);
input clk, reset, enable;
output [3:0] count;
reg [3:0] count;
always @ (posedge clk)
if (reset == 1'b1) begin
count <= 0;
end else if ( enable == 1'b1) begin
count <= count + 1;
end
endmodule

226
tests/asicworld/code_verilog_tutorial_counter_tb.v
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@ -1,113 +1,113 @@
///////////////////////////////////////////////////////////////////////////
// MODULE : counter_tb //
// TOP MODULE : -- //
// //
// PURPOSE : 4-bit up counter test bench //
// //
// DESIGNER : Deepak Kumar Tala //
// //
// Revision History //
// //
// DEVELOPMENT HISTORY : //
// Rev0.0 : Jan 03, 2003 //
// Initial Revision //
// //
///////////////////////////////////////////////////////////////////////////
module testbench;
reg clk, reset, enable;
wire [3:0] count;
reg dut_error;
counter U0 (
.clk (clk),
.reset (reset),
.enable (enable),
.count (count)
);
event reset_enable;
event terminate_sim;
initial
begin
$display ("###################################################");
clk = 0;
reset = 0;
enable = 0;
dut_error = 0;
end
always
#5 clk = !clk;
initial
begin
$dumpfile ("counter.vcd");
$dumpvars;
end
initial
@ (terminate_sim) begin
$display ("Terminating simulation");
if (dut_error == 0) begin
$display ("Simulation Result : PASSED");
end
else begin
$display ("Simulation Result : FAILED");
end
$display ("###################################################");
#1 $finish;
end
event reset_done;
initial
forever begin
@ (reset_enable);
@ (negedge clk)
$display ("Applying reset");
reset = 1;
@ (negedge clk)
reset = 0;
$display ("Came out of Reset");
-> reset_done;
end
initial begin
#10 -> reset_enable;
@ (reset_done);
@ (negedge clk);
enable = 1;
repeat (5)
begin
@ (negedge clk);
end
enable = 0;
#5 -> terminate_sim;
end
reg [3:0] count_compare;
always @ (posedge clk)
if (reset == 1'b1)
count_compare <= 0;
else if ( enable == 1'b1)
count_compare <= count_compare + 1;
always @ (negedge clk)
if (count_compare != count) begin
$display ("DUT ERROR AT TIME%d",$time);
$display ("Expected value %d, Got Value %d", count_compare, count);
dut_error = 1;
#5 -> terminate_sim;
end
endmodule
///////////////////////////////////////////////////////////////////////////
// MODULE : counter_tb //
// TOP MODULE : -- //
// //
// PURPOSE : 4-bit up counter test bench //
// //
// DESIGNER : Deepak Kumar Tala //
// //
// Revision History //
// //
// DEVELOPMENT HISTORY : //
// Rev0.0 : Jan 03, 2003 //
// Initial Revision //
// //
///////////////////////////////////////////////////////////////////////////
module testbench;
reg clk, reset, enable;
wire [3:0] count;
reg dut_error;
counter U0 (
.clk (clk),
.reset (reset),
.enable (enable),
.count (count)
);
event reset_enable;
event terminate_sim;
initial
begin
$display ("###################################################");
clk = 0;
reset = 0;
enable = 0;
dut_error = 0;
end
always
#5 clk = !clk;
initial
begin
$dumpfile ("counter.vcd");
$dumpvars;
end
initial
@ (terminate_sim) begin
$display ("Terminating simulation");
if (dut_error == 0) begin
$display ("Simulation Result : PASSED");
end
else begin
$display ("Simulation Result : FAILED");
end
$display ("###################################################");
#1 $finish;
end
event reset_done;
initial
forever begin
@ (reset_enable);
@ (negedge clk)
$display ("Applying reset");
reset = 1;
@ (negedge clk)
reset = 0;
$display ("Came out of Reset");
-> reset_done;
end
initial begin
#10 -> reset_enable;
@ (reset_done);
@ (negedge clk);
enable = 1;
repeat (5)
begin
@ (negedge clk);
end
enable = 0;
#5 -> terminate_sim;
end
reg [3:0] count_compare;
always @ (posedge clk)
if (reset == 1'b1)
count_compare <= 0;
else if ( enable == 1'b1)
count_compare <= count_compare + 1;
always @ (negedge clk)
if (count_compare != count) begin
$display ("DUT ERROR AT TIME%d",$time);
$display ("Expected value %d, Got Value %d", count_compare, count);
dut_error = 1;
#5 -> terminate_sim;
end
endmodule