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Merge 785cabcb0f into c21cd300a0

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KrystalDelusion 2025-06-03 01:08:27 +12:00 • committed by GitHub
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11 changed files with 72 additions and 101 deletions
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15
passes/proc/proc_arst.cc
View file

@ -288,17 +288,14 @@ struct ProcArstPass : public Pass {
extra_args(args, argidx, design); extra_args(args, argidx, design);
pool<Wire*> delete_initattr_wires; pool<Wire*> delete_initattr_wires;
for (auto mod : design->modules()) for (auto mod : design->all_selected_modules()) {
if (design->selected(mod)) {
SigMap assign_map(mod); SigMap assign_map(mod);
for (auto &proc_it : mod->processes) { for (auto proc : mod->selected_processes()) {
if (!design->selected(mod, proc_it.second)) proc_arst(mod, proc, assign_map);
continue;
proc_arst(mod, proc_it.second, assign_map);
if (global_arst.empty() || mod->wire(global_arst) == nullptr) if (global_arst.empty() || mod->wire(global_arst) == nullptr)
continue; continue;
std::vector<RTLIL::SigSig> arst_actions; std::vector<RTLIL::SigSig> arst_actions;
for (auto sync : proc_it.second->syncs) for (auto sync : proc->syncs)
if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn)
for (auto &act : sync->actions) { for (auto &act : sync->actions) {
RTLIL::SigSpec arst_sig, arst_val; RTLIL::SigSpec arst_sig, arst_val;
@ -312,7 +309,7 @@ struct ProcArstPass : public Pass {
} }
if (arst_sig.size()) { if (arst_sig.size()) {
log("Added global reset to process %s: %s <- %s\n", log("Added global reset to process %s: %s <- %s\n",
proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val)); proc->name.c_str(), log_signal(arst_sig), log_signal(arst_val));
arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val));
} }
} }
@ -321,7 +318,7 @@ struct ProcArstPass : public Pass {
sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1;
sync->signal = mod->wire(global_arst); sync->signal = mod->wire(global_arst);
sync->actions = arst_actions; sync->actions = arst_actions;
proc_it.second->syncs.push_back(sync); proc->syncs.push_back(sync);
} }
} }
} }

18
passes/proc/proc_clean.cc
View file

@ -208,19 +208,15 @@ struct ProcCleanPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto mod : design->modules()) { for (auto mod : design->all_selected_modules()) {
std::vector<RTLIL::Process *> delme; std::vector<RTLIL::Process *> delme;
if (!design->selected(mod)) for (auto proc : mod->selected_processes()) {
continue; proc_clean(mod, proc, total_count, quiet);
for (auto &proc_it : mod->processes) { if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 &&
if (!design->selected(mod, proc_it.second)) proc->root_case.actions.size() == 0) {
continue;
proc_clean(mod, proc_it.second, total_count, quiet);
if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
proc_it.second->root_case.actions.size() == 0) {
if (!quiet) if (!quiet)
log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str()); log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str());
delme.push_back(proc_it.second); delme.push_back(proc);
} }
} }
for (auto proc : delme) { for (auto proc : delme) {

8
passes/proc/proc_dff.cc
View file

@ -306,12 +306,10 @@ struct ProcDffPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto mod : design->modules()) for (auto mod : design->all_selected_modules()) {
if (design->selected(mod)) {
ConstEval ce(mod); ConstEval ce(mod);
for (auto &proc_it : mod->processes) for (auto proc : mod->selected_processes())
if (design->selected(mod, proc_it.second)) proc_dff(mod, proc, ce);
proc_dff(mod, proc_it.second, ce);
} }
} }
} ProcDffPass; } ProcDffPass;

9
passes/proc/proc_dlatch.cc
View file

@ -463,11 +463,10 @@ struct ProcDlatchPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto module : design->selected_modules()) { for (auto mod : design->all_selected_modules()) {
proc_dlatch_db_t db(module); proc_dlatch_db_t db(mod);
for (auto &proc_it : module->processes) for (auto proc : mod->selected_processes())
if (design->selected(module, proc_it.second)) proc_dlatch(db, proc);
proc_dlatch(db, proc_it.second);
db.fixup_muxes(); db.fixup_muxes();
} }
} }

8
passes/proc/proc_init.cc
View file

@ -91,12 +91,10 @@ struct ProcInitPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto mod : design->modules()) for (auto mod : design->all_selected_modules()) {
if (design->selected(mod)) {
SigMap sigmap(mod); SigMap sigmap(mod);
for (auto &proc_it : mod->processes) for (auto proc : mod->selected_processes())
if (design->selected(mod, proc_it.second)) proc_init(mod, sigmap, proc);
proc_init(mod, sigmap, proc_it.second);
} }
} }
} ProcInitPass; } ProcInitPass;

9
passes/proc/proc_memwr.cc
View file

@ -99,9 +99,9 @@ struct ProcMemWrPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto module : design->selected_modules()) { for (auto mod : design->all_selected_modules()) {
dict<IdString, int> next_port_id; dict<IdString, int> next_port_id;
for (auto cell : module->cells()) { for (auto cell : mod->cells()) {
if (cell->type.in(ID($memwr), ID($memwr_v2))) { if (cell->type.in(ID($memwr), ID($memwr_v2))) {
bool is_compat = cell->type == ID($memwr); bool is_compat = cell->type == ID($memwr);
IdString memid = cell->parameters.at(ID::MEMID).decode_string(); IdString memid = cell->parameters.at(ID::MEMID).decode_string();
@ -110,9 +110,8 @@ struct ProcMemWrPass : public Pass {
next_port_id[memid] = port_id + 1; next_port_id[memid] = port_id + 1;
} }
} }
for (auto &proc_it : module->processes) for (auto proc : mod->selected_processes())
if (design->selected(module, proc_it.second)) proc_memwr(mod, proc, next_port_id);
proc_memwr(module, proc_it.second, next_port_id);
} }
} }
} ProcMemWrPass; } ProcMemWrPass;

8
passes/proc/proc_mux.cc
View file

@ -468,11 +468,9 @@ struct ProcMuxPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto mod : design->modules()) for (auto mod : design->all_selected_modules())
if (design->selected(mod)) for (auto proc : mod->selected_processes())
for (auto &proc_it : mod->processes) proc_mux(mod, proc, ifxmode);
if (design->selected(mod, proc_it.second))
proc_mux(mod, proc_it.second, ifxmode);
} }
} ProcMuxPass; } ProcMuxPass;

11
passes/proc/proc_prune.cc
View file

@ -127,15 +127,10 @@ struct ProcPrunePass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto mod : design->modules()) { for (auto mod : design->all_selected_modules()) {
if (!design->selected(mod))
continue;
PruneWorker worker(mod); PruneWorker worker(mod);
for (auto &proc_it : mod->processes) { for (auto proc : mod->selected_processes())
if (!design->selected(mod, proc_it.second)) worker.do_process(proc);
continue;
worker.do_process(proc_it.second);
}
total_removed_count += worker.removed_count; total_removed_count += worker.removed_count;
total_promoted_count += worker.promoted_count; total_promoted_count += worker.promoted_count;
} }

14
passes/proc/proc_rmdead.cc
View file

@ -147,21 +147,17 @@ struct ProcRmdeadPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
int total_counter = 0; int total_counter = 0;
for (auto mod : design->modules()) { for (auto mod : design->all_selected_modules()) {
if (!design->selected(mod)) for (auto proc : mod->selected_processes()) {
continue;
for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second))
continue;
int counter = 0, full_case_counter = 0; int counter = 0, full_case_counter = 0;
for (auto switch_it : proc_it.second->root_case.switches) for (auto switch_it : proc->root_case.switches)
proc_rmdead(switch_it, counter, full_case_counter); proc_rmdead(switch_it, counter, full_case_counter);
if (counter > 0) if (counter > 0)
log("Removed %d dead cases from process %s in module %s.\n", counter, log("Removed %d dead cases from process %s in module %s.\n", counter,
log_id(proc_it.first), log_id(mod)); log_id(proc), log_id(mod));
if (full_case_counter > 0) if (full_case_counter > 0)
log("Marked %d switch rules as full_case in process %s in module %s.\n", log("Marked %d switch rules as full_case in process %s in module %s.\n",
full_case_counter, log_id(proc_it.first), log_id(mod)); full_case_counter, log_id(proc), log_id(mod));
total_counter += counter; total_counter += counter;
} }
} }

11
passes/proc/proc_rom.cc
View file

@ -243,15 +243,10 @@ struct ProcRomPass : public Pass {
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto mod : design->modules()) { for (auto mod : design->all_selected_modules()) {
if (!design->selected(mod))
continue;
RomWorker worker(mod); RomWorker worker(mod);
for (auto &proc_it : mod->processes) { for (auto proc : mod->selected_processes())
if (!design->selected(mod, proc_it.second)) worker.do_process(proc);
continue;
worker.do_process(proc_it.second);
}
total_count += worker.count; total_count += worker.count;
} }

6
passes/techmap/abc9_ops.cc
View file

@ -123,7 +123,7 @@ void check(RTLIL::Design *design, bool dff_mode)
log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", log_id(derived_type)); log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", log_id(derived_type));
if (derived_module->has_processes()) if (derived_module->has_processes())
Pass::call_on_module(design, derived_module, "proc"); Pass::call_on_module(design, derived_module, "proc -noopt");
bool found = false; bool found = false;
for (auto derived_cell : derived_module->cells()) { for (auto derived_cell : derived_module->cells()) {
@ -204,7 +204,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
if (!unmap_design->module(derived_type)) { if (!unmap_design->module(derived_type)) {
if (derived_module->has_processes()) if (derived_module->has_processes())
Pass::call_on_module(design, derived_module, "proc"); Pass::call_on_module(design, derived_module, "proc -noopt");
if (derived_module->get_bool_attribute(ID::abc9_flop)) { if (derived_module->get_bool_attribute(ID::abc9_flop)) {
for (auto derived_cell : derived_module->cells()) for (auto derived_cell : derived_module->cells())
@ -834,7 +834,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
holes_cell = holes_module->addCell(NEW_ID, cell->type); holes_cell = holes_module->addCell(NEW_ID, cell->type);
if (box_module->has_processes()) if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc"); Pass::call_on_module(design, box_module, "proc -noopt");
int box_inputs = 0; int box_inputs = 0;
for (auto port_name : box_ports.at(cell->type)) { for (auto port_name : box_ports.at(cell->type)) {