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ice40_dsp: add test

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This commit is contained in:
Eddie Hung 2020-01-17 15:38:26 -08:00
parent 4985318263
commit ad6c49fff1
1 changed files with 11 additions and 0 deletions
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tests/arch/ice40/ice40_dsp.ys Normal file
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read_verilog <<EOT
module top(input [15:0] a, b, output [31:0] o1, o2, o5);
SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1));
assign o2 = a * 16'd0;
wire [31:0] o3, o4;
SB_MAC16 m2 (.A(a), .B(b), .O(o3));
assign o4 = a * b;
SB_MAC16 m3 (.A(a), .B(b), .O(o5));
endmodule
EOT
ice40_dsp