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	Add retime test
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								tests/simple/retime.v
									
										
									
									
									
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								tests/simple/retime.v
									
										
									
									
									
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module retime_test(input clk, input [7:0] a, output z);
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    reg [7:0] ff = 8'hF5;
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    always @(posedge clk)
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        ff <= {ff[6:0], ^a};
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    assign z = ff[7];
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endmodule
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