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More yosys-smtbmc smtc features

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This commit is contained in:
Clifford Wolf 2016-08-24 23:18:29 +02:00
parent ee3e7a0e45
commit ad56ad44c3
5 changed files with 97 additions and 20 deletions
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5
examples/smtbmc/.gitignore vendored
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@ -1,9 +1,12 @@
demo1.smt2
demo1.yslog
demo2.smt2
demo2.smtc
demo2.vcd
demo2.yslog
demo2_tb
demo2_tb.smtc
demo2_tb.v
demo2_tb.vcd
demo3.smt2
demo3.vcd
demo3.yslog

15
examples/smtbmc/Makefile
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all: demo1 demo2
all: demo1 demo2 demo3
demo1: demo1.smt2
yosys-smtbmc --dump-vcd demo1.vcd demo1.smt2
yosys-smtbmc -i --dump-vcd demo1.vcd demo1.smt2
demo2: demo2.smt2
yosys-smtbmc -g --dump-vcd demo2.vcd --dump-vlogtb demo2_tb.v --dump-smtc demo2_tb.smtc demo2.smt2
yosys-smtbmc -g --dump-vcd demo2.vcd --dump-smtc demo2.smtc --dump-vlogtb demo2_tb.v demo2.smt2
iverilog -g2012 -o demo2_tb demo2_tb.v demo2.v
vvp demo2_tb +vcd=demo2_tb.vcd
demo3: demo3.smt2
yosys-smtbmc --dump-vcd demo3.vcd --smtc demo3.smtc demo3.smt2
demo1.smt2: demo1.v
yosys -ql demo1.yslog -p 'read_verilog -formal demo1.v; prep -top demo1 -nordff; write_smt2 -wires -mem -bv demo1.smt2'
demo2.smt2: demo2.v
yosys -ql demo2.yslog -p 'read_verilog -formal demo2.v; prep -top demo2 -nordff; write_smt2 -wires -mem -bv demo2.smt2'
demo3.smt2: demo3.v
yosys -ql demo3.yslog -p 'read_verilog -formal demo3.v; prep -top demo3 -nordff; write_smt2 -wires -mem -bv demo3.smt2'
clean:
rm -f demo1.yslog demo1.smt2 demo1.vcd
rm -f demo2.yslog demo2.smt2 demo2.vcd demo2_tb.v demo2_tb demo2_tb.vcd demo2_tb.smtc
rm -f demo2.yslog demo2.smt2 demo2.vcd demo2.smtc demo2_tb.v demo2_tb demo2_tb.vcd
rm -f demo3.yslog demo3.smt2 demo3.vcd
.PHONY: demo1 clean
.PHONY: demo1 demo2 demo3 clean

5
examples/smtbmc/demo3.smtc Normal file
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initial
assume [rst]
always -1
assert (= [-1:mem] [mem])

18
examples/smtbmc/demo3.v Normal file
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// Whatever the initial content of this memory is at reset, it will never change
// see demo3.smtc for assumptions and assertions
module demo3(input clk, rst, input [15:0] addr, output reg [31:0] data);
reg [31:0] mem [0:2**16-1];
reg [15:0] addr_q;
always @(posedge clk) begin
if (rst) begin
data <= mem[0] ^ 123456789;
addr_q <= 0;
end else begin
mem[addr_q] <= data ^ 123456789;
data <= mem[addr] ^ 123456789;
addr_q <= addr;
end
end
endmodule