mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

Merge pull request #2594 from zachjs/func-arg-width

Browse source 
verilog: fix sizing of constant args for tasks/functions
This commit is contained in:
whitequark 2021-02-23 21:46:16 +00:00 • committed by GitHub
commit ad2960adb7
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
10 changed files with 124 additions and 47 deletions
Download patch file Download diff file Expand all files Collapse all files

12
tests/verilog/func_arg_mismatch_1.ys Normal file
View file

@ -0,0 +1,12 @@
logger -expect error "Incompatible re-declaration of wire" 1
read_verilog -sv <<EOT
module top;
function automatic integer f;
input [0:0] inp;
integer inp;
f = inp;
endfunction
integer x, y;
initial x = f(y);
endmodule
EOT

12
tests/verilog/func_arg_mismatch_2.ys Normal file
View file

@ -0,0 +1,12 @@
logger -expect error "Incompatible re-declaration of constant function wire" 1
read_verilog -sv <<EOT
module top;
function automatic integer f;
input [0:0] inp;
integer inp;
f = inp;
endfunction
integer x;
initial x = f(0);
endmodule
EOT

12
tests/verilog/func_arg_mismatch_3.ys Normal file
View file

@ -0,0 +1,12 @@
logger -expect error "Incompatible re-declaration of wire" 1
read_verilog -sv <<EOT
module top;
function automatic integer f;
input [1:0] inp;
integer inp;
f = inp;
endfunction
integer x, y;
initial x = f(y);
endmodule
EOT

12
tests/verilog/func_arg_mismatch_4.ys Normal file
View file

@ -0,0 +1,12 @@
logger -expect error "Incompatible re-declaration of constant function wire" 1
read_verilog -sv <<EOT
module top;
function automatic integer f;
input [1:0] inp;
integer inp;
f = inp;
endfunction
integer x;
initial x = f(0);
endmodule
EOT