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Fix inout handling for -map option

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This commit is contained in:
Eddie Hung 2019-04-12 17:02:24 -07:00
parent d880f73c79
commit acf3f5694b
1 changed files with 30 additions and 10 deletions
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40
frontends/aiger/aigerparse.cc
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@ -439,7 +439,7 @@ next_line:
std::string type, symbol; std::string type, symbol;
int variable, index; int variable, index;
while (mf >> type >> variable >> index >> symbol) { while (mf >> type >> variable >> index >> symbol) {
RTLIL::IdString escaped_symbol = RTLIL::escape_id(symbol); RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
if (type == "input") { if (type == "input") {
log_assert(static_cast<unsigned>(variable) < inputs.size()); log_assert(static_cast<unsigned>(variable) < inputs.size());
RTLIL::Wire* wire = inputs[variable]; RTLIL::Wire* wire = inputs[variable];
@ -447,11 +447,11 @@ next_line:
log_assert(wire->port_input); log_assert(wire->port_input);
if (index == 0) if (index == 0)
module->rename(wire, escaped_symbol); module->rename(wire, escaped_s);
else if (index > 0) { else if (index > 0) {
module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
if (wideports) if (wideports)
wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
} }
} }
else if (type == "output") { else if (type == "output") {
@ -460,12 +460,32 @@ next_line:
log_assert(wire); log_assert(wire);
log_assert(wire->port_output); log_assert(wire->port_output);
if (index == 0) if (index == 0) {
module->rename(wire, escaped_symbol); if (escaped_s.ends_with("$inout.out")) {
else if (index > 0) { wire->port_output = false;
module->rename(wire, stringf("%s[%d]", escaped_symbol.c_str(), index)); RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
if (wideports) log_assert(in_wire);
wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); log_assert(in_wire->port_input && !in_wire->port_output);
in_wire->port_output = true;
module->connect(in_wire, wire);
}
else
module->rename(wire, escaped_s);
}
else if (index > 0) {
if (escaped_s.ends_with("$inout.out")) {
wire->port_output = false;
RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
log_assert(in_wire);
log_assert(in_wire->port_input && !in_wire->port_output);
in_wire->port_output = true;
module->connect(in_wire, wire);
}
else {
module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
if (wideports)
wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
}
} }
} }
else else