mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
Remove now-redundant opt_rmdff pass.
This commit is contained in:
Marcelina Kościelnicka
parent
9a4f420b4b
commit
acd8c5c205
2 changed files with 0 additions and 712 deletions
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@ -4,7 +4,6 @@ OBJS += passes/opt/opt_merge.o
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OBJS += passes/opt/opt_mem.o
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OBJS += passes/opt/opt_muxtree.o
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OBJS += passes/opt/opt_reduce.o
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OBJS += passes/opt/opt_rmdff.o
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OBJS += passes/opt/opt_dff.o
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OBJS += passes/opt/opt_share.o
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OBJS += passes/opt/opt_clean.o
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@ -1,711 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/satgen.h"
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#include "kernel/sigtools.h"
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#include <stdio.h>
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#include <stdlib.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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SigMap assign_map, dff_init_map;
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SigSet<RTLIL::Cell*> mux_drivers;
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dict<SigBit, RTLIL::Cell*> bit2driver;
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dict<SigBit, pool<SigBit>> init_attributes;
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bool keepdc;
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bool sat;
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void remove_init_attr(SigSpec sig)
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{
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for (auto bit : assign_map(sig))
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if (init_attributes.count(bit))
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for (auto wbit : init_attributes.at(bit))
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wbit.wire->attributes.at(ID::init)[wbit.offset] = State::Sx;
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}
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bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
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{
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SigSpec sig_set, sig_clr;
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State pol_set, pol_clr;
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if (cell->hasPort(ID::S))
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sig_set = cell->getPort(ID::S);
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if (cell->hasPort(ID::R))
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sig_clr = cell->getPort(ID::R);
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if (cell->hasPort(ID::SET))
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sig_set = cell->getPort(ID::SET);
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if (cell->hasPort(ID::CLR))
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sig_clr = cell->getPort(ID::CLR);
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log_assert(GetSize(sig_set) == GetSize(sig_clr));
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if (cell->type.begins_with("$_DFFSR_")) {
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pol_set = cell->type[9] == 'P' ? State::S1 : State::S0;
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pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0;
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} else
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if (cell->type.begins_with("$_DLATCHSR_")) {
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pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
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pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
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} else
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if (cell->type.in(ID($dffsr), ID($dlatchsr))) {
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pol_set = cell->parameters[ID::SET_POLARITY].as_bool() ? State::S1 : State::S0;
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pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool() ? State::S1 : State::S0;
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} else
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log_abort();
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State npol_set = pol_set == State::S0 ? State::S1 : State::S0;
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State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0;
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SigSpec sig_d = cell->getPort(ID::D);
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SigSpec sig_q = cell->getPort(ID::Q);
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bool did_something = false;
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bool proper_sr = false;
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bool used_pol_set = false;
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bool used_pol_clr = false;
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bool hasreset = false;
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Const reset_val;
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SigSpec sig_reset;
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for (int i = 0; i < GetSize(sig_set); i++)
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{
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SigBit s = sig_set[i], c = sig_clr[i];
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if (s != npol_set || c != npol_clr)
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hasreset = true;
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if (s == pol_set || c == pol_clr)
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{
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log("Constantly %s Q bit %s for SR cell %s (%s) from module %s.\n",
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s == pol_set ? "set" : "cleared", log_signal(sig_q[i]),
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log_id(cell), log_id(cell->type), log_id(mod));
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remove_init_attr(sig_q[i]);
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mod->connect(sig_q[i], s == pol_set ? State::S1 : State::S0);
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sig_set.remove(i);
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sig_clr.remove(i);
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sig_d.remove(i);
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sig_q.remove(i--);
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did_something = true;
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continue;
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}
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if (sig_reset.empty() && s.wire != nullptr) sig_reset = s;
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if (sig_reset.empty() && c.wire != nullptr) sig_reset = c;
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if (s.wire != nullptr && s != sig_reset) proper_sr = true;
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if (c.wire != nullptr && c != sig_reset) proper_sr = true;
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if ((s.wire == nullptr) != (c.wire == nullptr)) {
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if (s.wire != nullptr) used_pol_set = true;
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if (c.wire != nullptr) used_pol_clr = true;
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reset_val.bits.push_back(c.wire == nullptr ? State::S1 : State::S0);
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} else
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proper_sr = true;
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}
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if (!hasreset)
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proper_sr = false;
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if (GetSize(sig_set) == 0)
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{
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log("Removing %s (%s) from module %s.\n", log_id(cell), log_id(cell->type), log_id(mod));
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mod->remove(cell);
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return true;
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}
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if (cell->type.in(ID($dffsr), ID($dlatchsr)))
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{
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cell->setParam(ID::WIDTH, GetSize(sig_d));
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cell->setPort(ID::SET, sig_set);
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cell->setPort(ID::CLR, sig_clr);
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cell->setPort(ID::D, sig_d);
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cell->setPort(ID::Q, sig_q);
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}
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else
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{
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cell->setPort(ID::S, sig_set);
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cell->setPort(ID::R, sig_clr);
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cell->setPort(ID::D, sig_d);
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cell->setPort(ID::Q, sig_q);
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}
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if (proper_sr)
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return did_something;
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if (used_pol_set && used_pol_clr && pol_set != pol_clr)
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return did_something;
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if (cell->type == ID($dlatchsr))
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return did_something;
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State unified_pol = used_pol_set ? pol_set : pol_clr;
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if (cell->type == ID($dffsr))
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{
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if (hasreset)
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{
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log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod));
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cell->type = ID($adff);
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cell->setParam(ID::ARST_POLARITY, unified_pol);
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cell->setParam(ID::ARST_VALUE, reset_val);
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cell->setPort(ID::ARST, sig_reset);
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cell->unsetParam(ID::SET_POLARITY);
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cell->unsetParam(ID::CLR_POLARITY);
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cell->unsetPort(ID::SET);
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cell->unsetPort(ID::CLR);
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}
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else
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{
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log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod));
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cell->type = ID($dff);
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cell->unsetParam(ID::SET_POLARITY);
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cell->unsetParam(ID::CLR_POLARITY);
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cell->unsetPort(ID::SET);
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cell->unsetPort(ID::CLR);
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}
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return true;
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}
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if (!hasreset)
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{
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IdString new_type;
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if (cell->type.begins_with("$_DFFSR_"))
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new_type = stringf("$_DFF_%c_", cell->type[8]);
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else if (cell->type.begins_with("$_DLATCHSR_"))
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new_type = stringf("$_DLATCH_%c_", cell->type[11]);
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else
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log_abort();
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log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod));
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cell->type = new_type;
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cell->unsetPort(ID::S);
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cell->unsetPort(ID::R);
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return true;
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}
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return did_something;
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}
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bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
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{
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SigSpec sig_e;
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State on_state, off_state;
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if (dlatch->type == ID($dlatch)) {
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sig_e = assign_map(dlatch->getPort(ID::EN));
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on_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S1 : State::S0;
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off_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S0 : State::S1;
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} else
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if (dlatch->type == ID($_DLATCH_P_)) {
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sig_e = assign_map(dlatch->getPort(ID::E));
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on_state = State::S1;
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off_state = State::S0;
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} else
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if (dlatch->type == ID($_DLATCH_N_)) {
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sig_e = assign_map(dlatch->getPort(ID::E));
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on_state = State::S0;
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off_state = State::S1;
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} else
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log_abort();
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if (sig_e == off_state)
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{
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RTLIL::Const val_init;
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for (auto bit : dff_init_map(dlatch->getPort(ID::Q)))
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val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx);
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mod->connect(dlatch->getPort(ID::Q), val_init);
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goto delete_dlatch;
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}
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if (sig_e == on_state)
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{
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mod->connect(dlatch->getPort(ID::Q), dlatch->getPort(ID::D));
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goto delete_dlatch;
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}
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return false;
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delete_dlatch:
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log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod));
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remove_init_attr(dlatch->getPort(ID::Q));
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mod->remove(dlatch);
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return true;
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}
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bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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{
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RTLIL::SigSpec sig_d, sig_q, sig_c, sig_r, sig_e;
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RTLIL::Const val_cp, val_rp, val_rv, val_ep;
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if (dff->type == ID($_FF_)) {
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sig_d = dff->getPort(ID::D);
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sig_q = dff->getPort(ID::Q);
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}
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else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) {
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sig_d = dff->getPort(ID::D);
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sig_q = dff->getPort(ID::Q);
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sig_c = dff->getPort(ID::C);
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val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1);
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}
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else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 &&
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(dff->type[6] == 'N' || dff->type[6] == 'P') &&
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(dff->type[7] == 'N' || dff->type[7] == 'P') &&
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(dff->type[8] == '0' || dff->type[8] == '1')) {
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sig_d = dff->getPort(ID::D);
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sig_q = dff->getPort(ID::Q);
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sig_c = dff->getPort(ID::C);
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sig_r = dff->getPort(ID::R);
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val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
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val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
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val_rv = RTLIL::Const(dff->type[8] == '1', 1);
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}
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else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 &&
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(dff->type[7] == 'N' || dff->type[7] == 'P') &&
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(dff->type[8] == 'N' || dff->type[8] == 'P')) {
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sig_d = dff->getPort(ID::D);
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sig_q = dff->getPort(ID::Q);
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sig_c = dff->getPort(ID::C);
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sig_e = dff->getPort(ID::E);
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val_cp = RTLIL::Const(dff->type[7] == 'P', 1);
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val_ep = RTLIL::Const(dff->type[8] == 'P', 1);
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}
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else if (dff->type == ID($ff)) {
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sig_d = dff->getPort(ID::D);
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sig_q = dff->getPort(ID::Q);
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}
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else if (dff->type == ID($dff)) {
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sig_d = dff->getPort(ID::D);
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sig_q = dff->getPort(ID::Q);
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sig_c = dff->getPort(ID::CLK);
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val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
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}
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else if (dff->type == ID($dffe)) {
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sig_e = dff->getPort(ID::EN);
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sig_d = dff->getPort(ID::D);
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sig_q = dff->getPort(ID::Q);
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sig_c = dff->getPort(ID::CLK);
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val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
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val_ep = RTLIL::Const(dff->parameters[ID::EN_POLARITY].as_bool(), 1);
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}
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else if (dff->type == ID($adff)) {
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sig_d = dff->getPort(ID::D);
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sig_q = dff->getPort(ID::Q);
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sig_c = dff->getPort(ID::CLK);
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sig_r = dff->getPort(ID::ARST);
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val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
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val_rp = RTLIL::Const(dff->parameters[ID::ARST_POLARITY].as_bool(), 1);
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val_rv = dff->parameters[ID::ARST_VALUE];
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}
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else
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log_abort();
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assign_map.apply(sig_d);
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assign_map.apply(sig_q);
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assign_map.apply(sig_c);
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assign_map.apply(sig_r);
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bool has_init = false;
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RTLIL::Const val_init;
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for (auto bit : dff_init_map(sig_q).to_sigbit_vector()) {
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if (bit.wire == NULL || keepdc)
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has_init = true;
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val_init.bits.push_back(bit.wire == NULL ? bit.data : RTLIL::State::Sx);
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}
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if (dff->type.in(ID($ff), ID($dff)) && mux_drivers.has(sig_d)) {
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std::set<RTLIL::Cell*> muxes;
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mux_drivers.find(sig_d, muxes);
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for (auto mux : muxes) {
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RTLIL::SigSpec sig_a = assign_map(mux->getPort(ID::A));
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RTLIL::SigSpec sig_b = assign_map(mux->getPort(ID::B));
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if (sig_a == sig_q && sig_b.is_fully_const() && (!has_init || val_init == sig_b.as_const())) {
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mod->connect(sig_q, sig_b);
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goto delete_dff;
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}
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if (sig_b == sig_q && sig_a.is_fully_const() && (!has_init || val_init == sig_a.as_const())) {
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mod->connect(sig_q, sig_a);
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goto delete_dff;
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}
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}
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}
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// If clock is driven by a constant and (i) no reset signal
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// (ii) Q has no initial value
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// (iii) initial value is same as reset value
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if (!sig_c.empty() && sig_c.is_fully_const() && (!sig_r.size() || !has_init || val_init == val_rv)) {
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if (val_rv.bits.size() == 0)
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val_rv = val_init;
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// Q is permanently reset value or initial value
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mod->connect(sig_q, val_rv);
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goto delete_dff;
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}
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// If D is fully undefined and reset signal present and (i) Q has no initial value
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// (ii) initial value is same as reset value
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if (sig_d.is_fully_undef() && sig_r.size() && (!has_init || val_init == val_rv)) {
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// Q is permanently reset value
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mod->connect(sig_q, val_rv);
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goto delete_dff;
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}
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// If D is fully undefined and no reset signal and Q has an initial value
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if (sig_d.is_fully_undef() && !sig_r.size() && has_init) {
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// Q is permanently initial value
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mod->connect(sig_q, val_init);
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goto delete_dff;
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}
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// If D is fully constant and (i) no reset signal
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// (ii) reset value is same as constant D
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// and (a) has no initial value
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// (b) initial value same as constant D
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if (sig_d.is_fully_const() && (!sig_r.size() || val_rv == sig_d.as_const()) && (!has_init || val_init == sig_d.as_const())) {
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// Q is permanently D
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mod->connect(sig_q, sig_d);
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goto delete_dff;
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}
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// If D input is same as Q output and (i) no reset signal
|
||||
// (ii) no initial signal
|
||||
// (iii) initial value is same as reset value
|
||||
if (sig_d == sig_q && (sig_r.empty() || !has_init || val_init == val_rv)) {
|
||||
// Q is permanently reset value or initial value
|
||||
if (sig_r.size())
|
||||
mod->connect(sig_q, val_rv);
|
||||
else if (has_init)
|
||||
mod->connect(sig_q, val_init);
|
||||
goto delete_dff;
|
||||
}
|
||||
|
||||
// If reset signal is present, and is fully constant
|
||||
if (!sig_r.empty() && sig_r.is_fully_const())
|
||||
{
|
||||
// If reset value is permanently active or if reset is undefined
|
||||
if (sig_r == val_rp || sig_r.is_fully_undef()) {
|
||||
// Q is permanently reset value
|
||||
mod->connect(sig_q, val_rv);
|
||||
goto delete_dff;
|
||||
}
|
||||
|
||||
log("Removing unused reset from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
|
||||
|
||||
if (dff->type == ID($adff)) {
|
||||
dff->type = ID($dff);
|
||||
dff->unsetPort(ID::ARST);
|
||||
dff->unsetParam(ID::ARST_POLARITY);
|
||||
dff->unsetParam(ID::ARST_VALUE);
|
||||
return true;
|
||||
}
|
||||
|
||||
log_assert(dff->type.begins_with("$_DFF_"));
|
||||
dff->type = stringf("$_DFF_%c_", + dff->type[6]);
|
||||
dff->unsetPort(ID::R);
|
||||
}
|
||||
|
||||
// If enable signal is present, and is fully constant
|
||||
if (!sig_e.empty() && sig_e.is_fully_const())
|
||||
{
|
||||
// If enable value is permanently inactive
|
||||
if (sig_e != val_ep) {
|
||||
// Q is permanently initial value
|
||||
mod->connect(sig_q, val_init);
|
||||
goto delete_dff;
|
||||
}
|
||||
|
||||
log("Removing unused enable from %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
|
||||
|
||||
if (dff->type == ID($dffe)) {
|
||||
dff->type = ID($dff);
|
||||
dff->unsetPort(ID::EN);
|
||||
dff->unsetParam(ID::EN_POLARITY);
|
||||
return true;
|
||||
}
|
||||
|
||||
log_assert(dff->type.begins_with("$_DFFE_"));
|
||||
dff->type = stringf("$_DFF_%c_", + dff->type[7]);
|
||||
dff->unsetPort(ID::E);
|
||||
}
|
||||
|
||||
if (sat && has_init && (!sig_r.size() || val_init == val_rv))
|
||||
{
|
||||
bool removed_sigbits = false;
|
||||
|
||||
ezSatPtr ez;
|
||||
SatGen satgen(ez.get(), &assign_map);
|
||||
pool<Cell*> sat_cells;
|
||||
|
||||
std::function<void(Cell*)> sat_import_cell = [&](Cell *c) {
|
||||
if (!sat_cells.insert(c).second)
|
||||
return;
|
||||
if (!satgen.importCell(c))
|
||||
return;
|
||||
for (auto &conn : c->connections()) {
|
||||
if (!c->input(conn.first))
|
||||
continue;
|
||||
for (auto bit : assign_map(conn.second))
|
||||
if (bit2driver.count(bit))
|
||||
sat_import_cell(bit2driver.at(bit));
|
||||
}
|
||||
};
|
||||
|
||||
// For each register bit, try to prove that it cannot change from the initial value. If so, remove it
|
||||
for (int position = 0; position < GetSize(sig_d); position += 1) {
|
||||
RTLIL::SigBit q_sigbit = sig_q[position];
|
||||
RTLIL::SigBit d_sigbit = sig_d[position];
|
||||
|
||||
if ((!q_sigbit.wire) || (!d_sigbit.wire))
|
||||
continue;
|
||||
|
||||
if (!bit2driver.count(d_sigbit))
|
||||
continue;
|
||||
|
||||
sat_import_cell(bit2driver.at(d_sigbit));
|
||||
|
||||
RTLIL::State sigbit_init_val = val_init[position];
|
||||
if (sigbit_init_val != State::S0 && sigbit_init_val != State::S1)
|
||||
continue;
|
||||
|
||||
int init_sat_pi = satgen.importSigSpec(sigbit_init_val).front();
|
||||
int q_sat_pi = satgen.importSigBit(q_sigbit);
|
||||
int d_sat_pi = satgen.importSigBit(d_sigbit);
|
||||
|
||||
// Try to find out whether the register bit can change under some circumstances
|
||||
bool counter_example_found = ez->solve(ez->IFF(q_sat_pi, init_sat_pi), ez->NOT(ez->IFF(d_sat_pi, init_sat_pi)));
|
||||
|
||||
// If the register bit cannot change, we can replace it with a constant
|
||||
if (!counter_example_found)
|
||||
{
|
||||
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0,
|
||||
position, log_id(dff), log_id(dff->type), log_id(mod));
|
||||
|
||||
SigSpec tmp = dff->getPort(ID::D);
|
||||
tmp[position] = sigbit_init_val;
|
||||
dff->setPort(ID::D, tmp);
|
||||
|
||||
removed_sigbits = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (removed_sigbits) {
|
||||
handle_dff(mod, dff);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return false;
|
||||
|
||||
delete_dff:
|
||||
log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
|
||||
remove_init_attr(dff->getPort(ID::Q));
|
||||
mod->remove(dff);
|
||||
|
||||
for (auto &entry : bit2driver)
|
||||
if (entry.second == dff)
|
||||
bit2driver.erase(entry.first);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
struct OptRmdffPass : public Pass {
|
||||
OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" opt_rmdff [-keepdc] [-sat] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass identifies flip-flops with constant inputs and replaces them with\n");
|
||||
log("a constant driver.\n");
|
||||
log("\n");
|
||||
log(" -sat\n");
|
||||
log(" additionally invoke SAT solver to detect and remove flip-flops (with \n");
|
||||
log(" non-constant inputs) that can also be replaced with a constant driver\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
int total_count = 0, total_initdrv = 0;
|
||||
log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
|
||||
|
||||
keepdc = false;
|
||||
sat = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-keepdc") {
|
||||
keepdc = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-sat") {
|
||||
sat = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
pool<SigBit> driven_bits;
|
||||
dict<SigBit, State> init_bits;
|
||||
|
||||
assign_map.set(module);
|
||||
dff_init_map.set(module);
|
||||
mux_drivers.clear();
|
||||
bit2driver.clear();
|
||||
init_attributes.clear();
|
||||
|
||||
for (auto wire : module->wires())
|
||||
{
|
||||
if (wire->attributes.count(ID::init) != 0) {
|
||||
Const initval = wire->attributes.at(ID::init);
|
||||
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
|
||||
if (initval[i] == State::S0 || initval[i] == State::S1)
|
||||
dff_init_map.add(SigBit(wire, i), initval[i]);
|
||||
for (int i = 0; i < GetSize(wire); i++) {
|
||||
SigBit wire_bit(wire, i), mapped_bit = assign_map(wire_bit);
|
||||
if (mapped_bit.wire) {
|
||||
init_attributes[mapped_bit].insert(wire_bit);
|
||||
if (i < GetSize(initval))
|
||||
init_bits[mapped_bit] = initval[i];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (wire->port_input) {
|
||||
for (auto bit : assign_map(wire))
|
||||
driven_bits.insert(bit);
|
||||
}
|
||||
}
|
||||
|
||||
std::vector<RTLIL::IdString> dff_list;
|
||||
std::vector<RTLIL::IdString> dffsr_list;
|
||||
std::vector<RTLIL::IdString> dlatch_list;
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
for (auto &conn : cell->connections()) {
|
||||
bool is_output = cell->output(conn.first);
|
||||
if (is_output || !cell->known())
|
||||
for (auto bit : assign_map(conn.second)) {
|
||||
if (is_output)
|
||||
bit2driver[bit] = cell;
|
||||
driven_bits.insert(bit);
|
||||
}
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($mux), ID($pmux))) {
|
||||
if (cell->getPort(ID::A).size() == cell->getPort(ID::B).size())
|
||||
mux_drivers.insert(assign_map(cell->getPort(ID::Y)), cell);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!design->selected(module, cell))
|
||||
continue;
|
||||
|
||||
if (cell->type.in(ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
|
||||
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_), ID($dffsr),
|
||||
ID($_DLATCHSR_NNN_), ID($_DLATCHSR_NNP_), ID($_DLATCHSR_NPN_), ID($_DLATCHSR_NPP_),
|
||||
ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_), ID($dlatchsr)))
|
||||
dffsr_list.push_back(cell->name);
|
||||
|
||||
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_),
|
||||
ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
|
||||
ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
|
||||
ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
|
||||
ID($ff), ID($dff), ID($dffe), ID($adff)))
|
||||
dff_list.push_back(cell->name);
|
||||
|
||||
if (cell->type.in(ID($dlatch), ID($_DLATCH_P_), ID($_DLATCH_N_)))
|
||||
dlatch_list.push_back(cell->name);
|
||||
}
|
||||
|
||||
for (auto &id : dffsr_list) {
|
||||
if (module->cell(id) != nullptr &&
|
||||
handle_dffsr(module, module->cells_[id]))
|
||||
total_count++;
|
||||
}
|
||||
|
||||
for (auto &id : dff_list) {
|
||||
if (module->cell(id) != nullptr &&
|
||||
handle_dff(module, module->cells_[id]))
|
||||
total_count++;
|
||||
}
|
||||
|
||||
for (auto &id : dlatch_list) {
|
||||
if (module->cell(id) != nullptr &&
|
||||
handle_dlatch(module, module->cells_[id]))
|
||||
total_count++;
|
||||
}
|
||||
|
||||
SigSpec const_init_sigs;
|
||||
|
||||
for (auto bit : init_bits)
|
||||
if (!driven_bits.count(bit.first))
|
||||
const_init_sigs.append(bit.first);
|
||||
|
||||
const_init_sigs.sort_and_unify();
|
||||
|
||||
for (SigSpec sig : const_init_sigs.chunks())
|
||||
{
|
||||
Const val;
|
||||
|
||||
for (auto bit : sig)
|
||||
val.bits.push_back(init_bits.at(bit));
|
||||
|
||||
log("Promoting init spec %s = %s to constant driver in module %s.\n",
|
||||
log_signal(sig), log_signal(val), log_id(module));
|
||||
|
||||
module->connect(sig, val);
|
||||
remove_init_attr(sig);
|
||||
total_initdrv++;
|
||||
}
|
||||
}
|
||||
|
||||
assign_map.clear();
|
||||
mux_drivers.clear();
|
||||
bit2driver.clear();
|
||||
init_attributes.clear();
|
||||
|
||||
if (total_count || total_initdrv)
|
||||
design->scratchpad_set_bool("opt.did_something", true);
|
||||
|
||||
if (total_initdrv)
|
||||
log("Promoted %d init specs to constant drivers.\n", total_initdrv);
|
||||
|
||||
if (total_count)
|
||||
log("Replaced %d DFF cells.\n", total_count);
|
||||
}
|
||||
} OptRmdffPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Add table
Add a link
Reference in a new issue