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tests: Centralize test collection and Makefile generation

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Xiretza 2020-09-16 17:59:37 +02:00
parent c6ff947f6b
commit acd47bbd52
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16 changed files with 136 additions and 222 deletions
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2
tests/techmap/mem_simple_4x1_runtest.sh
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@ -1,6 +1,6 @@
#!/bin/bash
set -ev
set -e
../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v