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Docs: Test new pass help with chformal

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Krystine Sherwin 2025-03-21 10:24:28 +13:00
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103
passes/cmds/chformal.cc
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@ -70,62 +70,59 @@ static bool is_triggered_check_cell(RTLIL::Cell * cell)
} }
struct ChformalPass : public Pass { struct ChformalPass : public Pass {
ChformalPass() : Pass("chformal", "change formal constraints of the design") { } ChformalPass() : Pass("chformal", "change formal constraints of the design", {
void help() override
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| .signature = "chformal [types] [mode] [options] [selection]",
log("\n"); .description = "Make changes to the formal constraints of the design. The [types] options the type of "
log(" chformal [types] [mode] [options] [selection]\n"); "constraint to operate on. If none of the following options are given, the command "
log("\n"); "will operate on all constraint types:",
log("Make changes to the formal constraints of the design. The [types] options\n"); .options = {
log("the type of constraint to operate on. If none of the following options are\n"); {"-assert $assert cells, representing assert(...) constraints"
log("given, the command will operate on all constraint types:\n"); "\n-assume $assume cells, representing assume(...) constraints"
log("\n"); "\n-live $live cells, representing assert(s_eventually ...)"
log(" -assert $assert cells, representing assert(...) constraints\n"); "\n-fair $fair cells, representing assume(s_eventually ...)"
log(" -assume $assume cells, representing assume(...) constraints\n"); "\n-cover $cover cells, representing cover() statements", ""},
log(" -live $live cells, representing assert(s_eventually ...)\n"); {"Additionally chformal will operate on $check cells corresponding to the selected constraint "
log(" -fair $fair cells, representing assume(s_eventually ...)\n"); "types.", ""},
log(" -cover $cover cells, representing cover() statements\n"); }
log("\n"); },
log(" Additionally chformal will operate on $check cells corresponding to the\n"); {
log(" selected constraint types.\n"); .description = "Exactly one of the following modes must be specified:",
log("\n"); .options = {
log("Exactly one of the following modes must be specified:\n"); {"-remove",
log("\n"); "remove the cells and thus constraints from the design"},
log(" -remove\n"); {"-early",
log(" remove the cells and thus constraints from the design\n"); "bypass FFs that only delay the activation of a constraint. When inputs "
log("\n"); "of the bypassed FFs do not remain stable between clock edges, this may "
log(" -early\n"); "result in unexpected behavior."
log(" bypass FFs that only delay the activation of a constraint. When inputs\n"); },
log(" of the bypassed FFs do not remain stable between clock edges, this may\n"); {"-delay <N>",
log(" result in unexpected behavior.\n"); "delay activation of the constraint by <N> clock cycles"
log("\n"); },
log(" -delay <N>\n"); {"-skip <N>",
log(" delay activation of the constraint by <N> clock cycles\n"); "ignore activation of the constraint in the first <N> clock cycles"
log("\n"); },
log(" -skip <N>\n"); {"-coverenable",
log(" ignore activation of the constraint in the first <N> clock cycles\n"); "add cover statements for the enable signals of the constraints"
log("\n");
log(" -coverenable\n");
log(" add cover statements for the enable signals of the constraints\n");
log("\n");
#ifdef YOSYS_ENABLE_VERIFIC #ifdef YOSYS_ENABLE_VERIFIC
log(" Note: For the Verific frontend it is currently not guaranteed that a\n"); "\n\nNote: For the Verific frontend it is currently not guaranteed that a "
log(" reachable SVA statement corresponds to an active enable signal.\n"); "reachable SVA statement corresponds to an active enable signal."
log("\n");
#endif #endif
log(" -assert2assume\n"); },
log(" -assume2assert\n"); {"-assert2assume"
log(" -live2fair\n"); "\n-assume2assert"
log(" -fair2live\n"); "\n-live2fair"
log(" change the roles of cells as indicated. these options can be combined\n"); "\n-fair2live",
log("\n"); "change the roles of cells as indicated. these options can be combined"
log(" -lower\n"); },
log(" convert each $check cell into an $assert, $assume, $live, $fair or\n"); {"-lower",
log(" $cover cell. If the $check cell contains a message, also produce a\n"); "convert each $check cell into an $assert, $assume, $live, $fair or "
log(" $print cell.\n"); "$cover cell. If the $check cell contains a message, also produce a "
log("\n"); "$print cell."
} },
}
},
}) { }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
bool assert2assume = false; bool assert2assume = false;