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Address all comments

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This commit is contained in:
Jason Xu 2025-03-07 00:57:39 -05:00
parent 8ec96ec806
commit ac31bad656
1 changed files with 36 additions and 36 deletions
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42
frontends/verilog/verilog_frontend.cc
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@ -674,27 +674,7 @@ struct VerilogDefines : public Pass {
}
} VerilogDefines;
struct VerilogFileList : public Pass {
VerilogFileList() : Pass("read_verilog_file_list", "Parse a Verilog file list") {}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" read_verilog_file_list [options]\n");
log("\n");
log("Parse a Verilog file list, and pass the list of Verilog files to read_verilog command.\n");
log("\n");
log(" -F file_list_path\n");
log(" File list file contains list of Verilog files to be parsed, any\n");
log(" path is treated relative to the file list file\n");
log("\n");
log(" -f file_list_path\n");
log(" File list file contains list of Verilog files to be parsed, any\n");
log(" path is treated relative to current working directroy\n");
log("\n");
}
void parse_file_list(const std::string &file_list_path, RTLIL::Design *design, bool relative_to_file_list_path)
static void parse_file_list(const std::string &file_list_path, RTLIL::Design *design, bool relative_to_file_list_path)
{
std::ifstream flist(file_list_path);
if (!flist.is_open()) {
@ -730,6 +710,26 @@ struct VerilogFileList : public Pass {
flist.close();
}
struct VerilogFileList : public Pass {
VerilogFileList() : Pass("read_verilog_file_list", "Parse a Verilog file list") {}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" read_verilog_file_list [options]\n");
log("\n");
log("Parse a Verilog file list, and pass the list of Verilog files to read_verilog command.\n");
log("\n");
log(" -F file_list_path\n");
log(" File list file contains list of Verilog files to be parsed, any\n");
log(" path is treated relative to the file list file\n");
log("\n");
log(" -f file_list_path\n");
log(" File list file contains list of Verilog files to be parsed, any\n");
log(" path is treated relative to current working directroy\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
size_t argidx;