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Fix for non-pow2 width muxes

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This commit is contained in:
Eddie Hung 2019-04-22 14:26:13 -07:00
parent 75b96b1aff
commit ac1e13819e
1 changed files with 18 additions and 9 deletions
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17
techlibs/xilinx/cells_map.v
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@ -157,6 +157,15 @@ module \$shiftx (A, B, Y);
parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
function integer first_B_nonzero;
integer i;
begin
for (i = B_WIDTH-1; i >= 0; i--)
if (_TECHMAP_CONSTMSK_B_[i] == 1'b0 || _TECHMAP_CONSTVAL_B_ != 1'b0)
first_B_nonzero = i;
end
endfunction
generate generate
genvar i, j; genvar i, j;
if (B_SIGNED) begin if (B_SIGNED) begin
@ -167,12 +176,12 @@ module \$shiftx (A, B, Y);
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
end end
else if (Y_WIDTH > 1) begin else if (Y_WIDTH > 1) begin
wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_bitty = B/Y_WIDTH; localparam inc = first_B_nonzero();
for (i = 0; i < Y_WIDTH; i++) begin for (i = 0; i < Y_WIDTH; i++) begin
wire [A_WIDTH/Y_WIDTH-1:0] A_i; wire [A_WIDTH/Y_WIDTH-1:0] A_i;
for (j = 0; j < A_WIDTH/Y_WIDTH; j++) for (j = 0; j*(1<<inc)+i < A_WIDTH; j++)
assign A_i[j] = A[j*Y_WIDTH+i]; assign A_i[j] = A[j*(1<<inc)+i];
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_bitty), .Y(Y[i])); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH(B_WIDTH-inc), .Y_WIDTH(1'b1)) bitblast (.A(A_i), .B(B[B_WIDTH-1:inc]), .Y(Y[i]));
end end
end end
else if (B_WIDTH < 3) begin else if (B_WIDTH < 3) begin