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cxxrtl: use IdString::isPublic(). NFC.

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This commit is contained in:
whitequark 2020-12-13 00:54:12 +00:00
parent 080f311040
commit ac1a78923a
1 changed files with 4 additions and 4 deletions
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8
backends/cxxrtl/cxxrtl_backend.cc
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@ -211,7 +211,7 @@ bool is_ff_cell(RTLIL::IdString type)
bool is_internal_cell(RTLIL::IdString type) bool is_internal_cell(RTLIL::IdString type)
{ {
return type[0] == '$' && !type.begins_with("$paramod"); return !type.isPublic() && !type.begins_with("$paramod");
} }
bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell) bool is_cxxrtl_blackbox_cell(const RTLIL::Cell *cell)
@ -1665,7 +1665,7 @@ struct CxxrtlWorker {
inc_indent(); inc_indent();
f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n"; f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (wire->name[0] != '\\') if (!wire->name.isPublic())
continue; continue;
if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0)) if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
continue; continue;
@ -1743,7 +1743,7 @@ struct CxxrtlWorker {
} }
if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) { if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
for (auto &memory_it : module->memories) { for (auto &memory_it : module->memories) {
if (memory_it.first[0] != '\\') if (!memory_it.first.isPublic())
continue; continue;
f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second)); f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
f << ", debug_item(" << mangle(memory_it.second) << ", "; f << ", debug_item(" << mangle(memory_it.second) << ", ";
@ -2338,7 +2338,7 @@ struct CxxrtlWorker {
// Note that the information collected here can't be used for optimizing the netlist: debug information queries // Note that the information collected here can't be used for optimizing the netlist: debug information queries
// are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold. // are pure and run on a design in a stable state, which allows assumptions that do not otherwise hold.
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (wire->name[0] != '\\') if (!wire->name.isPublic())
continue; continue;
if (!unbuffered_wires[wire]) if (!unbuffered_wires[wire])
continue; continue;