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Progress in equiv_simple

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This commit is contained in:
Clifford Wolf 2015-01-21 23:59:58 +00:00
parent 74e1de1fac
commit abf8398216
2 changed files with 110 additions and 41 deletions
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7
kernel/rtlil.cc
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@ -1055,8 +1055,11 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
log_assert(new_mod->refcount_wires_ == 0);
log_assert(new_mod->refcount_cells_ == 0);
new_mod->connections_ = connections_;
new_mod->attributes = attributes;
for (auto &conn : connections_)
new_mod->connect(conn);
for (auto &attr : attributes)
new_mod->attributes[attr.first] = attr.second;
for (auto &it : wires_)
new_mod->addWire(it.first, it.second);