Replace 010 and 012 with pdf

Comment out the body text and instead include just the abstract and a download link.
Also orphan the pages so they aren't accessible except by direct link, or via search.

docs/source/appendix.rst

@@ -9,9 +9,6 @@ Appendix
 	appendix/auxlibs
 	appendix/auxprogs
 
-	appendix/APPNOTE_010_Verilog_to_BLIF.rst 
-	appendix/APPNOTE_012_Verilog_to_BTOR.rst
-
 	bib
 
 .. toctree::

docs/source/appendix/APPNOTE_010_Verilog_to_BLIF.rst

@@ -1,7 +1,37 @@
+:orphan:
+
 ====================================
 010: Converting Verilog to BLIF page
 ====================================
 
+Abstract
+========
+
+Verilog-2005 is a powerful Hardware Description Language (HDL) that can be used
+to easily create complex designs from small HDL code. It is the preferred method
+of design entry for many designers.
+
+The Berkeley Logic Interchange Format (BLIF) is a simple file format for
+exchanging sequential logic between programs. It is easy to generate and easy to
+parse and is therefore the preferred method of design entry for many authors of
+logic synthesis tools.
+
+Yosys is a feature-rich Open-Source Verilog synthesis tool that can be used to
+bridge the gap between the two file formats. It implements most of Verilog-2005
+and thus can be used to import modern behavioral Verilog designs into BLIF-based
+design flows without dependencies on proprietary synthesis tools.
+
+The scope of Yosys goes of course far beyond Verilog logic synthesis. But it is
+a useful and important feature and this Application Note will focus on this
+aspect of Yosys.
+
+Download
+========
+
+This document was originally published in April 2015:
+:download:`Converting Verilog to BLIF PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
+
+..
    Installation
    ============
 

docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst

@@ -1,7 +1,27 @@
+:orphan:
+
 ====================================
 012: Converting Verilog to BTOR page
 ====================================
 
+Abstract
+========
+
+Verilog-2005 is a powerful Hardware Description Language (HDL) that can be used
+to easily create complex designs from small HDL code. BTOR is a bit-precise
+word-level format for model checking. It is a simple format and easy to parse.
+It allows to model the model checking problem over the theory of bit-vectors
+with one-dimensional arrays, thus enabling to model Verilog designs with
+registers and memories. Yosys is an Open-Source Verilog synthesis tool that can
+be used to convert Verilog designs with simple assertions to BTOR format.
+
+Download
+========
+
+This document was originally published in November 2013: 
+:download:`Converting Verilog to BTOR PDF</_downloads/APPNOTE_012_Verilog_to_BTOR.pdf>`
+
+..
    Installation
    ============