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Use ABC to convert from AIGER to Verilog

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This commit is contained in:
Eddie Hung 2019-06-07 11:06:57 -07:00
parent ebe29b6659
commit abc40924ed
1 changed files with 3 additions and 2 deletions
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5
tests/tools/autotest.sh
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@ -146,9 +146,10 @@ do
rm -f ${bn}_ref.fir rm -f ${bn}_ref.fir
if [[ "$ext" == "v" ]]; then if [[ "$ext" == "v" ]]; then
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
else else
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} cp ../${fn} ${bn}_ref.${ext}
frontend="verilog -noblackbox"
fi fi
if [ ! -f ../${bn}_tb.v ]; then if [ ! -f ../${bn}_tb.v ]; then