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read_aiger to also rename 0 index lut when wideports
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01f8d50ba2
commit
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1 changed files with 14 additions and 2 deletions
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@ -162,9 +162,15 @@ void AigerReader::parse_aiger()
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int width = wp.second + 1;
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int width = wp.second + 1;
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RTLIL::Wire *wire = module->wire(name);
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RTLIL::Wire *wire = module->wire(name);
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if (wire)
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if (wire) {
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RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
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module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
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module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
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if (driver)
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module->rename(driver, stringf("%slut", wire->name.c_str()));
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}
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// Do not make ports with a mix of input/output into
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// Do not make ports with a mix of input/output into
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// wide ports
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// wide ports
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bool port_input = false, port_output = false;
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bool port_input = false, port_output = false;
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@ -408,9 +414,15 @@ void AigerReader::parse_xaiger()
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int width = wp.second + 1;
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int width = wp.second + 1;
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RTLIL::Wire *wire = module->wire(name);
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RTLIL::Wire *wire = module->wire(name);
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if (wire)
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if (wire) {
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RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str()));
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module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
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module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
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if (driver)
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module->rename(driver, stringf("%slut", wire->name.c_str()));
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}
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// Do not make ports with a mix of input/output into
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// Do not make ports with a mix of input/output into
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// wide ports
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// wide ports
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bool port_input = false, port_output = false;
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bool port_input = false, port_output = false;
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