From 2b97f197927780e36bd0c61161ce0a3aaf45e627 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Fri, 2 Jan 2026 17:45:21 +0530 Subject: [PATCH 1/3] verific: add support for relaxed checking option in VerificPass --- frontends/verific/verific.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5790e92f0..4c61c9ac0 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3688,6 +3688,10 @@ struct VerificPass : public Pass { veri_file::AddLOption(args[++argidx].c_str()); continue; } + if (args[argidx] == "-set_relaxed_checking") { + VeriNode::SetRelaxedChecking(0); + continue; + } #endif break; } From e24243e8d0abb0af5d8e4d3da2e5c47ff43adcf7 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Sun, 4 Jan 2026 01:31:17 +0530 Subject: [PATCH 2/3] set 1 --- frontends/verific/verific.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 4c61c9ac0..16e150bd2 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3689,7 +3689,7 @@ struct VerificPass : public Pass { continue; } if (args[argidx] == "-set_relaxed_checking") { - VeriNode::SetRelaxedChecking(0); + VeriNode::SetRelaxedChecking(1); continue; } #endif From cf6d89b6ad7db8e8fc56e7eda46c17da17b0f64a Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Sun, 4 Jan 2026 01:46:55 +0530 Subject: [PATCH 3/3] fix --- frontends/verific/verific.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 16e150bd2..9bfb1752b 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3688,15 +3688,16 @@ struct VerificPass : public Pass { veri_file::AddLOption(args[++argidx].c_str()); continue; } - if (args[argidx] == "-set_relaxed_checking") { - VeriNode::SetRelaxedChecking(1); - continue; - } #endif break; } #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + if (GetSize(args) > argidx && args[argidx] == "-set_relaxed_checking") { + VeriNode::SetRelaxedChecking(1); + continue; + } + if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED;