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https://github.com/YosysHQ/yosys
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cxxrtl: make eval() and commit() inline in blackboxes.
This change is a preparation for template blackboxes. It has no effect on current generated code.
This commit is contained in:
whitequark
parent
2b88d9a3fe
commit
ab4297c326
1 changed files with 103 additions and 82 deletions
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@ -1241,86 +1241,8 @@ struct CxxrtlWorker {
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}
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}
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void dump_module_intf(RTLIL::Module *module)
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void dump_eval_method(RTLIL::Module *module)
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{
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dump_attrs(module);
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f << "struct " << mangle(module) << " : public module {\n";
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inc_indent();
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if (module->get_bool_attribute(ID(cxxrtl.blackbox))) {
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for (auto wire : module->wires()) {
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if (wire->port_id != 0)
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dump_wire(wire, /*is_local=*/false);
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}
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f << "\n";
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} else {
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for (auto wire : module->wires())
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dump_wire(wire, /*is_local=*/false);
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f << "\n";
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bool has_memories = false;
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for (auto memory : module->memories) {
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dump_memory(module, memory.second);
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has_memories = true;
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}
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if (has_memories)
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f << "\n";
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bool has_cells = false;
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for (auto cell : module->cells()) {
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if (is_internal_cell(cell->type))
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continue;
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dump_attrs(cell);
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RTLIL::Module *cell_module = module->design->module(cell->type);
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log_assert(cell_module != nullptr);
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if (cell_module->get_bool_attribute(ID(cxxrtl.blackbox))) {
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f << indent << "std::unique_ptr<" << mangle(cell_module) << "> " << mangle(cell) << " = ";
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f << mangle(cell_module) << "::create(" << escape_cxx_string(cell->name.str()) << ", ";
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if (!cell->parameters.empty()) {
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f << "parameter_map({\n";
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inc_indent();
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for (auto param : cell->parameters) {
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// All blackbox parameters should be in the public namespace already; strip leading slash
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// to make it more convenient for blackbox implementations.
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log_assert(param.first.begins_with("\\"));
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f << indent << "{ " << escape_cxx_string(param.first.str().substr(1)) << ", ";
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if (param.second.flags & RTLIL::CONST_FLAG_REAL) {
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f << std::showpoint << std::stod(param.second.decode_string()) << std::noshowpoint;
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} else if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
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f << escape_cxx_string(param.second.decode_string());
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} else {
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f << param.second.as_int(/*is_signed=*/param.second.flags & RTLIL::CONST_FLAG_SIGNED);
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if (!(param.second.flags & RTLIL::CONST_FLAG_SIGNED))
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f << "u";
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}
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f << " },\n";
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}
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dec_indent();
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f << indent << "})";
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} else {
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f << "parameter_map()";
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}
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f << ");\n";
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} else {
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f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
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}
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has_cells = true;
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}
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if (has_cells)
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f << "\n";
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}
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f << indent << "void eval() override;\n";
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f << indent << "bool commit() override;\n";
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if (module->get_bool_attribute(ID(cxxrtl.blackbox))) {
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f << "\n";
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f << indent << "static std::unique_ptr<" << mangle(module) << "> ";
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f << "create(std::string name, parameter_map parameters);\n";
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}
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dec_indent();
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f << "}; // struct " << mangle(module) << "\n";
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f << "\n";
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}
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void dump_module_impl(RTLIL::Module *module)
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{
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f << "void " << mangle(module) << "::eval() {\n";
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inc_indent();
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if (!module->get_bool_attribute(ID(cxxrtl.blackbox))) {
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for (auto wire : module->wires())
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@ -1348,10 +1270,10 @@ struct CxxrtlWorker {
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}
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}
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dec_indent();
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f << "}\n";
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f << "\n";
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}
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f << "bool " << mangle(module) << "::commit() {\n";
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void dump_commit_method(RTLIL::Module *module)
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{
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inc_indent();
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f << indent << "bool changed = false;\n";
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for (auto wire : module->wires()) {
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@ -1406,6 +1328,105 @@ struct CxxrtlWorker {
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}
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f << indent << "return changed;\n";
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dec_indent();
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}
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void dump_module_intf(RTLIL::Module *module)
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{
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dump_attrs(module);
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if (module->get_bool_attribute(ID(cxxrtl.blackbox))) {
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f << "struct " << mangle(module) << " : public module {\n";
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inc_indent();
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for (auto wire : module->wires()) {
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if (wire->port_id != 0)
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dump_wire(wire, /*is_local=*/false);
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}
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f << "\n";
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f << indent << "void eval() override {\n";
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dump_eval_method(module);
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f << indent << "}\n";
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f << "\n";
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f << indent << "bool commit() override {\n";
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dump_commit_method(module);
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f << indent << "}\n";
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f << "\n";
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f << indent << "static std::unique_ptr<" << mangle(module) << "> ";
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f << "create(std::string name, parameter_map parameters);\n";
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dec_indent();
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f << "}; // struct " << mangle(module) << "\n";
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f << "\n";
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} else {
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f << "struct " << mangle(module) << " : public module {\n";
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inc_indent();
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for (auto wire : module->wires())
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dump_wire(wire, /*is_local=*/false);
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f << "\n";
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bool has_memories = false;
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for (auto memory : module->memories) {
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dump_memory(module, memory.second);
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has_memories = true;
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}
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if (has_memories)
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f << "\n";
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bool has_cells = false;
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for (auto cell : module->cells()) {
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if (is_internal_cell(cell->type))
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continue;
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dump_attrs(cell);
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RTLIL::Module *cell_module = module->design->module(cell->type);
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log_assert(cell_module != nullptr);
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if (cell_module->get_bool_attribute(ID(cxxrtl.blackbox))) {
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f << indent << "std::unique_ptr<" << mangle(cell_module) << "> " << mangle(cell) << " = ";
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f << mangle(cell_module) << "::create(" << escape_cxx_string(cell->name.str()) << ", ";
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if (!cell->parameters.empty()) {
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f << "parameter_map({\n";
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inc_indent();
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for (auto param : cell->parameters) {
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// All blackbox parameters should be in the public namespace already; strip leading slash
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// to make it more convenient for blackbox implementations.
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log_assert(param.first.begins_with("\\"));
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f << indent << "{ " << escape_cxx_string(param.first.str().substr(1)) << ", ";
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if (param.second.flags & RTLIL::CONST_FLAG_REAL) {
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f << std::showpoint << std::stod(param.second.decode_string()) << std::noshowpoint;
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} else if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
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f << escape_cxx_string(param.second.decode_string());
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} else {
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f << param.second.as_int(/*is_signed=*/param.second.flags & RTLIL::CONST_FLAG_SIGNED);
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if (!(param.second.flags & RTLIL::CONST_FLAG_SIGNED))
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f << "u";
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}
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f << " },\n";
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}
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dec_indent();
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f << indent << "})";
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} else {
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f << "parameter_map()";
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}
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f << ");\n";
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} else {
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f << indent << mangle(cell_module) << " " << mangle(cell) << ";\n";
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}
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has_cells = true;
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}
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if (has_cells)
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f << "\n";
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f << indent << "void eval() override;\n";
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f << indent << "bool commit() override;\n";
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dec_indent();
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f << "}; // struct " << mangle(module) << "\n";
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f << "\n";
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}
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}
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void dump_module_impl(RTLIL::Module *module)
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{
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if (module->get_bool_attribute(ID(cxxrtl.blackbox)))
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return;
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f << "void " << mangle(module) << "::eval() {\n";
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dump_eval_method(module);
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f << "}\n";
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f << "\n";
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f << "bool " << mangle(module) << "::commit() {\n";
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dump_commit_method(module);
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f << "}\n";
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f << "\n";
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}
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