diff --git a/kernel/constids.inc b/kernel/constids.inc
index 61c9b3a8c..cfd12e3fb 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -833,6 +833,7 @@ X(abcgroup)
 X(acc_fir)
 X(acc_fir_i)
 X(add_carry)
+X(aiger2_zbuf)
 X(allconst)
 X(allseq)
 X(always_comb)
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index dda3858da..e7cf8c637 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1652,7 +1652,7 @@ static void replace_zbufs(Design *design)
 				if (sig[i] == State::Sz) {
 					Wire *w = mod->addWire(NEW_ID);
 					Cell *ud = mod->addCell(NEW_ID, ID($tribuf));
-					ud->set_bool_attribute(ID(aiger2_zbuf));
+					ud->set_bool_attribute(ID::aiger2_zbuf);
 					ud->setParam(ID::WIDTH, 1);
 					ud->setPort(ID::Y, w);
 					ud->setPort(ID::EN, State::S0);
diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc
index 0afabce11..9850ff609 100644
--- a/passes/techmap/abc_new.cc
+++ b/passes/techmap/abc_new.cc
@@ -50,6 +50,17 @@ struct AbcNewPass : public ScriptPass {
 		experimental();
 	}
 
+	void on_register() override
+	{
+		RTLIL::constpad["abc_new.script.speed"] = "+&st; &dch -r;" \
+			"&nf; &st; &syn2; &if -g -K 6; &synch2 -r;" \
+			"&nf; &st; &syn2; &if -g -K 6; &synch2 -r;" \
+			"&nf; &st; &syn2; &if -g -K 6; &synch2 -r;" \
+			"&nf; &st; &syn2; &if -g -K 6; &synch2 -r;" \
+			"&nf; &st; &syn2; &if -g -K 6; &synch2 -r;" \
+			"&nf";
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -110,6 +121,11 @@ struct AbcNewPass : public ScriptPass {
 		}
 		extra_args(args, argidx, d);
 
+		// If no script provided, use a default.
+		if (abc_exe_options.find("-script") == std::string::npos) {
+			d->scratchpad_set_string("abc9.script", RTLIL::constpad["abc_new.script.speed"]);
+		}
+
 		log_header(d, "Executing ABC_NEW pass.\n");
 		log_push();
 		run_script(d, run_from, run_to);
diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc
index 409b07964..f7cdcbd12 100644
--- a/techlibs/gatemate/synth_gatemate.cc
+++ b/techlibs/gatemate/synth_gatemate.cc
@@ -69,7 +69,8 @@ struct SynthGateMatePass : public ScriptPass
 		log("        do not use CC_MX{8,4} multiplexer cells in output netlist.\n");
 		log("\n");
 		log("    -luttree\n");
-		log("        use new LUT tree mapping approach (EXPERIMENTAL).\n");
+		log("        use LUT tree mapping for output to nextpnr. Do not use this if targeting\n");
+		log("        legacy p_r.\n");
 		log("\n");
 		log("    -dff\n");
 		log("        run 'abc' with -dff option\n");
@@ -77,6 +78,9 @@ struct SynthGateMatePass : public ScriptPass
 		log("    -retime\n");
 		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
+		log("    -abc_new\n");
+		log("        use 'abc_new' instead of 'abc' for mapping. (EXPERIMENTAL)\n");
+		log("\n");
 		log("    -noiopad\n");
 		log("        disable I/O buffer insertion (useful for hierarchical or \n");
 		log("        out-of-context flows).\n");
@@ -90,7 +94,7 @@ struct SynthGateMatePass : public ScriptPass
 	}
 
 	string top_opt, vlog_file, json_file;
-	bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf;
+	bool noflatten, nobram, noaddf, nomult, nomx4, nomx8, luttree, dff, retime, noiopad, noclkbuf, abc_new;
 
 	void clear_flags() override
 	{
@@ -108,6 +112,7 @@ struct SynthGateMatePass : public ScriptPass
 		retime = false;
 		noiopad = false;
 		noclkbuf = false;
+		abc_new = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
@@ -182,6 +187,10 @@ struct SynthGateMatePass : public ScriptPass
 				noclkbuf = true;
 				continue;
 			}
+			if (args[argidx] == "-abc_new") {
+				abc_new = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -313,7 +322,11 @@ struct SynthGateMatePass : public ScriptPass
 				if (dff) {
 					abc_args += " -dff";
 				}
-				run("abc " + abc_args, "(with -luttree)");
+				if (abc_new) {
+					run("abc_new " + abc_args, "(with -luttree and -abc_new)");
+				} else {
+					run("abc " + abc_args, "(with -luttree, without -abc_new)");
+				}
 				run("techmap -map +/gatemate/lut_tree_map.v", "(with -luttree)");
 				run("gatemate_foldinv", "(with -luttree)");
 				run("techmap -map +/gatemate/inv_map.v", "(with -luttree)");
diff --git a/tests/arch/gatemate/add_sub.ys b/tests/arch/gatemate/add_sub.ys
index bf261ba5a..6720e08a0 100644
--- a/tests/arch/gatemate/add_sub.ys
+++ b/tests/arch/gatemate/add_sub.ys
@@ -1,9 +1,29 @@
 read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
+design -save orig
+
 equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 8 t:CC_ADDF
 select -assert-max 4 t:CC_LUT1
 select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D
+
+design -load orig
+
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:CC_ADDF
+select -assert-max 4 t:CC_LUT1
+select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D
+
+design -load orig
+
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:CC_ADDF
+select -assert-max 4 t:CC_LUT1
+select -assert-none t:CC_ADDF t:CC_LUT1 %% t:* %D
diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys
index b2ded6e9d..0a80a4b48 100644
--- a/tests/arch/gatemate/adffs.ys
+++ b/tests/arch/gatemate/adffs.ys
@@ -31,6 +31,28 @@ select -assert-count 1 t:CC_DFF
 select -assert-max 1 t:CC_LUT2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
 
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-max 1 t:CC_LUT2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-max 1 t:CC_LUT2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
+
 design -load read
 hierarchy -top ndffnr
 proc
@@ -41,3 +63,25 @@ select -assert-count 1 t:CC_BUFG
 select -assert-count 1 t:CC_DFF
 select -assert-max 1 t:CC_LUT2
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-max 1 t:CC_LUT2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_BUFG
+select -assert-count 1 t:CC_DFF
+select -assert-max 1 t:CC_LUT2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 %% t:* %D
diff --git a/tests/arch/gatemate/counter.ys b/tests/arch/gatemate/counter.ys
index 77ed858b3..8aa04e5cb 100644
--- a/tests/arch/gatemate/counter.ys
+++ b/tests/arch/gatemate/counter.ys
@@ -2,6 +2,9 @@ read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten
+
+design -save orig
+
 equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
@@ -10,3 +13,25 @@ select -assert-count 8 t:CC_ADDF
 select -assert-count 1 t:CC_BUFG
 select -assert-count 8 t:CC_DFF
 select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load orig
+
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8 t:CC_ADDF
+select -assert-count 1 t:CC_BUFG
+select -assert-count 8 t:CC_DFF
+select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D
+
+design -load orig
+
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 8 t:CC_ADDF
+select -assert-count 1 t:CC_BUFG
+select -assert-count 8 t:CC_DFF
+select -assert-none t:CC_ADDF t:CC_BUFG t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/fsm.ys b/tests/arch/gatemate/fsm.ys
index 506862c90..8af1a0a47 100644
--- a/tests/arch/gatemate/fsm.ys
+++ b/tests/arch/gatemate/fsm.ys
@@ -3,6 +3,8 @@ hierarchy -top fsm
 proc
 flatten
 
+design -save orig
+
 equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad
 async2sync
 miter -equiv -make_assert -flatten gold gate miter
@@ -18,3 +20,42 @@ select -assert-max 5 t:CC_LUT2
 select -assert-max 6 t:CC_LUT3
 select -assert-max 9 t:CC_LUT4
 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D
+
+design -load orig
+
+equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+stat
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:CC_BUFG
+select -assert-count 6 t:CC_DFF
+select -assert-max 2 t:CC_LUT1
+select -assert-count 1 t:CC_LUT2
+select -assert-max 14 t:CC_L2T4
+select -assert-max 5 t:CC_L2T5
+select -assert-max 1 t:CC_MX2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 t:CC_MX2 %% t:* %D
+
+design -load orig
+
+equiv_opt -run :prove -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new
+async2sync
+miter -equiv -make_assert -flatten gold gate miter
+stat
+sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:CC_BUFG
+select -assert-count 6 t:CC_DFF
+select -assert-count 2 t:CC_LUT2
+select -assert-count 9 t:CC_L2T4
+select -assert-count 6 t:CC_L2T5
+select -assert-count 1 t:CC_MX2
+select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 t:CC_MX2 %% t:* %D
diff --git a/tests/arch/gatemate/latches.ys b/tests/arch/gatemate/latches.ys
index 5f64c6db5..a044bf5d6 100644
--- a/tests/arch/gatemate/latches.ys
+++ b/tests/arch/gatemate/latches.ys
@@ -27,3 +27,23 @@ cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:CC_DLT
 select -assert-max 2 t:CC_LUT3
 select -assert-none t:CC_DLT t:CC_LUT3 %% t:* %D
+
+design -load read
+hierarchy -top latchsr
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_DLT
+select -assert-max 2 t:CC_L2T4
+select -assert-none t:CC_DLT t:CC_L2T4 %% t:* %D
+
+design -load read
+hierarchy -top latchsr
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_DLT
+select -assert-max 2 t:CC_L2T4
+select -assert-none t:CC_DLT t:CC_L2T4 %% t:* %D
diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys
index 026406bc8..e6204cdca 100644
--- a/tests/arch/gatemate/logic.ys
+++ b/tests/arch/gatemate/logic.ys
@@ -1,6 +1,9 @@
 read_verilog ../common/logic.v
 hierarchy -top top
 proc
+
+design -save orig
+
 equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
@@ -8,3 +11,23 @@ select -assert-max 1 t:CC_LUT1
 select -assert-max 6 t:CC_LUT2
 select -assert-max 2 t:CC_LUT4
 select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_LUT4 %% t:* %D
+
+design -load orig
+
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_LUT1
+select -assert-count 6 t:CC_LUT2
+select -assert-count 2 t:CC_L2T4
+select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D
+
+design -load orig
+
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_LUT1
+select -assert-count 6 t:CC_LUT2
+select -assert-count 2 t:CC_L2T4
+select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D
diff --git a/tests/arch/gatemate/luttrees.ys b/tests/arch/gatemate/luttrees.ys
index 545643226..f3a61ee60 100644
--- a/tests/arch/gatemate/luttrees.ys
+++ b/tests/arch/gatemate/luttrees.ys
@@ -11,3 +11,24 @@ cd luttrees # Constrain all select calls below inside the top module
 select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
 select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
 
+design -load read
+
+hierarchy -top luttrees
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd luttrees # Constrain all select calls below inside the top module
+
+select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
+select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
+
+design -load read
+
+hierarchy -top luttrees
+proc
+equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd luttrees # Constrain all select calls below inside the top module
+
+select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
+select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
diff --git a/tests/arch/gatemate/mul.ys b/tests/arch/gatemate/mul.ys
index ded5fe729..ef2255a76 100644
--- a/tests/arch/gatemate/mul.ys
+++ b/tests/arch/gatemate/mul.ys
@@ -31,3 +31,29 @@ select -assert-count 1 t:CC_BUFG
 select -assert-max 18 t:CC_LUT4
 select -assert-count 18 t:CC_DFF
 select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT4 t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top mul_unsigned_sync
+proc
+equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_unsigned_sync # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MULT
+select -assert-count 1 t:CC_BUFG
+select -assert-count 18 t:CC_LUT2
+select -assert-count 18 t:CC_MX2
+select -assert-count 18 t:CC_DFF
+select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT2 t:CC_MX2 t:CC_DFF %% t:* %D
+
+design -load read
+hierarchy -top mul_unsigned_sync
+proc
+# equiv_opt -assert -async2sync -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check (fails)
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_unsigned_sync # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_MULT
+select -assert-count 1 t:CC_BUFG
+select -assert-count 18 t:CC_LUT2
+select -assert-count 18 t:CC_MX2
+select -assert-count 18 t:CC_DFF
+select -assert-none t:CC_MULT t:CC_BUFG t:CC_LUT2 t:CC_MX2 t:CC_DFF %% t:* %D
diff --git a/tests/arch/gatemate/mux.ys b/tests/arch/gatemate/mux.ys
index 320ff33d7..51c3b5daf 100644
--- a/tests/arch/gatemate/mux.ys
+++ b/tests/arch/gatemate/mux.ys
@@ -12,6 +12,25 @@ select -assert-max 2 t:CC_LUT4
 select -assert-max 1 t:CC_MX2
 select -assert-none t:CC_LUT2 t:CC_LUT4 t:CC_MX2 %% t:* %D
 
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 3 t:CC_MX2
+select -assert-none t:CC_MX2 %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:CC_LUT1
+select -assert-count 3 t:CC_MX2
+select -assert-none t:CC_LUT1 t:CC_MX2 %% t:* %D
+
 design -load read
 hierarchy -top mux8
 proc
@@ -22,3 +41,21 @@ select -assert-max 1 t:CC_LUT3
 select -assert-max 5 t:CC_LUT4
 select -assert-max 1 t:CC_MX2
 select -assert-none t:CC_LUT3 t:CC_LUT4 t:CC_MX2 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 7 t:CC_MX2
+select -assert-none t:CC_MX2 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 7 t:CC_MX2
+select -assert-none t:CC_MX2 %% t:* %D
diff --git a/tests/techmap/abc_speed_gia_only.script b/tests/techmap/abc_speed_gia_only.script
deleted file mode 100644
index d3730fdb5..000000000
--- a/tests/techmap/abc_speed_gia_only.script
+++ /dev/null
@@ -1,28 +0,0 @@
-&st
-&dch -r
-&nf
-&st
-&syn2
-&if -g -K 6
-&synch2 -r
-&nf
-&st
-&syn2
-&if -g -K 6
-&synch2 -r
-&nf
-&st
-&syn2
-&if -g -K 6
-&synch2 -r
-&nf
-&st
-&syn2
-&if -g -K 6
-&synch2 -r
-&nf
-&st
-&syn2
-&if -g -K 6
-&synch2 -r
-&nf
diff --git a/tests/techmap/xaiger2-5169.ys b/tests/techmap/xaiger2-5169.ys
index 110f17346..1678d56ac 100644
--- a/tests/techmap/xaiger2-5169.ys
+++ b/tests/techmap/xaiger2-5169.ys
@@ -57,4 +57,4 @@ endmodule
 EOF
 
 logger -expect error "Malformed design" 1
-abc_new -script abc_speed_gia_only.script -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib
+abc_new -liberty ../../tests/liberty/normal.lib -liberty ../../tests/liberty/dff.lib