mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-10 17:25:49 +00:00
Code Activity

rtlil: enable single-bit vector wires

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit ab112b9b6b
12 changed files with 121 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

20
tests/verilog/sbvector.ys Normal file
View file

@ -0,0 +1,20 @@
read_verilog <<EOT
module foo(
output o,
input [0:0] i1,
input i2
);
assign o = i1 ^ i2;
endmodule
EOT
logger -expect log "wire width 1 input 2 \\i1" 1
logger -expect log "wire input 3 \\i2" 1
dump
logger -check-expected
write_verilog verilog_sbvector.out
!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
!grep -qF 'input [0:0] i1;' verilog_sbvector.out
!grep -qF 'wire i2;' verilog_sbvector.out
!grep -qF 'input i2;' verilog_sbvector.out