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rtlil: enable single-bit vector wires

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This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit ab112b9b6b
12 changed files with 121 additions and 9 deletions
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3
frontends/rtlil/rtlil_parser.y
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@ -188,6 +188,9 @@ wire_stmt:
wire_options:
wire_options TOK_WIDTH TOK_INT {
current_wire->width = $3;
// Width 1 specified -> single-bit vector rather than scalar
if (current_wire->width == 1)
current_wire->sbvector = true;
} |
wire_options TOK_WIDTH TOK_INVALID {
rtlil_frontend_yyerror("RTLIL error: invalid wire width");