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rtlil: enable single-bit vector wires

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This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit ab112b9b6b
12 changed files with 121 additions and 9 deletions
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11
frontends/json/jsonparse.cc
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@ -345,6 +345,12 @@ void json_import(Design *design, string &modname, JsonNode *node)
port_wire->upto = val->data_number != 0;
}
if (port_node->data_dict.count("sbvector") != 0) {
JsonNode *val = port_node->data_dict.at("sbvector");
if (val->type == 'N')
port_wire->sbvector = val->data_number != 0;
}
if (port_node->data_dict.count("signed") != 0) {
JsonNode *val = port_node->data_dict.at("signed");
if (val->type == 'N')
@ -442,6 +448,11 @@ void json_import(Design *design, string &modname, JsonNode *node)
if (val->type == 'N')
wire->upto = val->data_number != 0;
}
if (net_node->data_dict.count("sbvector") != 0) {
JsonNode *val = net_node->data_dict.at("sbvector");
if (val->type == 'N')
wire->sbvector = val->data_number != 0;
}
if (net_node->data_dict.count("offset") != 0) {
JsonNode *val = net_node->data_dict.at("offset");