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rtlil: enable single-bit vector wires

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This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit ab112b9b6b
12 changed files with 121 additions and 9 deletions
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6
frontends/ast/genrtlil.cc
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@ -1445,7 +1445,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_id = port_id;
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
if (wire->width != 1)
wire->upto = range_swapped;
else
wire->sbvector = is_sbvector;
wire->is_signed = is_signed;
for (auto &attr : attributes) {