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rtlil: enable single-bit vector wires

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This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit ab112b9b6b
12 changed files with 121 additions and 9 deletions
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2
frontends/ast/ast.cc
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@ -350,6 +350,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
fprintf(f, " port=%d", port_id);
if (range_valid || range_left != -1 || range_right != 0)
fprintf(f, " %srange=[%d:%d]%s", range_swapped ? "swapped_" : "", range_left, range_right, range_valid ? "" : "!");
if (is_sbvector)
fprintf(f, " vector");
if (integer != 0)
fprintf(f, " int=%u", (int)integer);
if (realvalue != 0)