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rtlil: enable single-bit vector wires

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This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit ab112b9b6b
12 changed files with 121 additions and 9 deletions
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2
frontends/ast/ast.cc
View file

@ -350,6 +350,8 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
fprintf(f, " port=%d", port_id);
if (range_valid || range_left != -1 || range_right != 0)
fprintf(f, " %srange=[%d:%d]%s", range_swapped ? "swapped_" : "", range_left, range_right, range_valid ? "" : "!");
if (is_sbvector)
fprintf(f, " vector");
if (integer != 0)
fprintf(f, " int=%u", (int)integer);
if (realvalue != 0)

2
frontends/ast/ast.h
View file

@ -192,7 +192,7 @@ namespace AST
// node content - most of it is unused in most node types
std::string str;
std::vector<RTLIL::State> bits;
bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized, is_custom_type;
bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, is_sbvector, was_checked, is_unsized, is_custom_type;
int port_id, range_left, range_right;
uint32_t integer;
double realvalue;

6
frontends/ast/genrtlil.cc
View file

@ -1445,7 +1445,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_id = port_id;
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
if (wire->width != 1)
wire->upto = range_swapped;
else
wire->sbvector = is_sbvector;
wire->is_signed = is_signed;
for (auto &attr : attributes) {

3
frontends/ast/simplify.cc
View file

@ -2084,6 +2084,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
std::swap(range_left, range_right);
range_swapped = force_upto;
}
if (range_left == range_right)
is_sbvector = true;
}
} else {
if (!range_valid)
@ -2092,6 +2094,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
range_swapped = false;
range_left = 0;
range_right = 0;
is_sbvector = false;
}
}

11
frontends/json/jsonparse.cc
View file

@ -345,6 +345,12 @@ void json_import(Design *design, string &modname, JsonNode *node)
port_wire->upto = val->data_number != 0;
}
if (port_node->data_dict.count("sbvector") != 0) {
JsonNode *val = port_node->data_dict.at("sbvector");
if (val->type == 'N')
port_wire->sbvector = val->data_number != 0;
}
if (port_node->data_dict.count("signed") != 0) {
JsonNode *val = port_node->data_dict.at("signed");
if (val->type == 'N')
@ -442,6 +448,11 @@ void json_import(Design *design, string &modname, JsonNode *node)
if (val->type == 'N')
wire->upto = val->data_number != 0;
}
if (net_node->data_dict.count("sbvector") != 0) {
JsonNode *val = net_node->data_dict.at("sbvector");
if (val->type == 'N')
wire->sbvector = val->data_number != 0;
}
if (net_node->data_dict.count("offset") != 0) {
JsonNode *val = net_node->data_dict.at("offset");

3
frontends/rtlil/rtlil_parser.y
View file

@ -188,6 +188,9 @@ wire_stmt:
wire_options:
wire_options TOK_WIDTH TOK_INT {
current_wire->width = $3;
// Width 1 specified -> single-bit vector rather than scalar
if (current_wire->width == 1)
current_wire->sbvector = true;
} |
wire_options TOK_WIDTH TOK_INVALID {
rtlil_frontend_yyerror("RTLIL error: invalid wire width");