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rtlil: enable single-bit vector wires

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This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit ab112b9b6b
12 changed files with 121 additions and 9 deletions
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10
backends/rtlil/rtlil_backend.cc
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@ -130,10 +130,14 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
wire->driverCell()->name.c_str(), wire->driverPort().c_str());
}
f << stringf("%s" "wire ", indent.c_str());
if (wire->width != 1)
if (wire->width == 1) {
if (wire->sbvector)
f << stringf("width %d ", wire->width);
} else {
f << stringf("width %d ", wire->width);
if (wire->upto)
f << stringf("upto ");
if (wire->upto)
f << stringf("upto ");
}
if (wire->start_offset != 0)
f << stringf("offset %d ", wire->start_offset);
if (wire->port_input && !wire->port_output)