mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-05-11 09:44:44 +00:00
Code Activity

rtlil: enable single-bit vector wires

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-05-06 12:02:00 +02:00
parent f60bbe64ac
commit ab112b9b6b
12 changed files with 121 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

13
backends/json/json.cc
View file

@ -178,8 +178,10 @@ struct JsonWriter
f << stringf(" \"direction\": \"%s\",\n", w->port_input ? w->port_output ? "inout" : "input" : "output");
if (w->start_offset)
f << stringf(" \"offset\": %d,\n", w->start_offset);
if (w->upto)
if (w->width != 1 && w->upto)
f << stringf(" \"upto\": 1,\n");
if (w->width == 1 && w->sbvector)
f << stringf(" \"sbvector\": 1,\n");
if (w->is_signed)
f << stringf(" \"signed\": %d,\n", w->is_signed);
f << stringf(" \"bits\": %s\n", get_bits(w).c_str());
@ -270,8 +272,10 @@ struct JsonWriter
f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
if (w->start_offset)
f << stringf(" \"offset\": %d,\n", w->start_offset);
if (w->upto)
if (w->width != 1 && w->upto)
f << stringf(" \"upto\": 1,\n");
if (w->width == 1 && w->sbvector)
f << stringf(" \"sbvector\": 1,\n");
if (w->is_signed)
f << stringf(" \"signed\": %d,\n", w->is_signed);
f << stringf(" \"attributes\": {");
@ -403,10 +407,12 @@ struct JsonBackend : public Backend {
log(" \"bits\": <bit_vector>\n");
log(" \"offset\": <the lowest bit index in use, if non-0>\n");
log(" \"upto\": <1 if the port bit indexing is MSB-first>\n");
log(" \"sbvector\": <1 if a single-bit port is a vector, not a scalar>\n");
log(" \"signed\": <1 if the port is signed>\n");
log(" }\n");
log("\n");
log("The \"offset\" and \"upto\" fields are skipped if their value would be 0.\n");
log("The \"offset\", \"upto\", and \"sbvector\" fields are skipped\n");
log("if their value would be 0.\n");
log("They don't affect connection semantics, and are only used to preserve original\n");
log("HDL bit indexing.\n");
log("And <cell_details> is:\n");
@ -453,6 +459,7 @@ struct JsonBackend : public Backend {
log(" \"bits\": <bit_vector>\n");
log(" \"offset\": <the lowest bit index in use, if non-0>\n");
log(" \"upto\": <1 if the port bit indexing is MSB-first>\n");
log(" \"sbvector\": <1 if a single-bit port is a vector, not a scalar>\n");
log(" \"signed\": <1 if the port is signed>\n");
log(" }\n");
log("\n");

10
backends/rtlil/rtlil_backend.cc
View file

@ -130,10 +130,14 @@ void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
wire->driverCell()->name.c_str(), wire->driverPort().c_str());
}
f << stringf("%s" "wire ", indent.c_str());
if (wire->width != 1)
if (wire->width == 1) {
if (wire->sbvector)
f << stringf("width %d ", wire->width);
} else {
f << stringf("width %d ", wire->width);
if (wire->upto)
f << stringf("upto ");
if (wire->upto)
f << stringf("upto ");
}
if (wire->start_offset != 0)
f << stringf("offset %d ", wire->start_offset);
if (wire->port_input && !wire->port_output)

3
backends/verilog/verilog_backend.cc
View file

@ -419,6 +419,9 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset);
else
range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset);
} else {
if (wire->sbvector)
range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
}
if (wire->port_input && !wire->port_output)
f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());