mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-05 02:40:25 +00:00
Proc: Use selections consistently
All `proc_*` passes now use the same module and process for loops, using `design->all_selected_modules()` and `mod->selected_processes()` respectively. This simplifies the code, and makes the couple `proc_*` passes that were ignoring boxed modules stop doing that (which seems to have been erroneous rather than intentional).
This commit is contained in:
parent
545753cc5a
commit
ab0e3cc05f
10 changed files with 69 additions and 98 deletions
|
@ -208,19 +208,15 @@ struct ProcCleanPass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto mod : design->modules()) {
|
||||
for (auto mod : design->all_selected_modules()) {
|
||||
std::vector<RTLIL::Process *> delme;
|
||||
if (!design->selected(mod))
|
||||
continue;
|
||||
for (auto &proc_it : mod->processes) {
|
||||
if (!design->selected(mod, proc_it.second))
|
||||
continue;
|
||||
proc_clean(mod, proc_it.second, total_count, quiet);
|
||||
if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
|
||||
proc_it.second->root_case.actions.size() == 0) {
|
||||
for (auto proc : mod->selected_processes()) {
|
||||
proc_clean(mod, proc, total_count, quiet);
|
||||
if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 &&
|
||||
proc->root_case.actions.size() == 0) {
|
||||
if (!quiet)
|
||||
log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
|
||||
delme.push_back(proc_it.second);
|
||||
log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str());
|
||||
delme.push_back(proc);
|
||||
}
|
||||
}
|
||||
for (auto proc : delme) {
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue