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Rename abc_* names/attributes to more precisely be abc9_*
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Eddie Hung
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34 changed files with 313 additions and 305 deletions
190
techlibs/xilinx/abc9_model.v
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190
techlibs/xilinx/abc9_model.v
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// ============================================================================
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// Box containing MUXF7.[AB] + MUXF8,
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// Necessary to make these an atomic unit so that
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// ABC cannot optimise just one of the MUXF7 away
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// and expect to save on its delay
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(* abc9_box_id = 3, lib_whitebox *)
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module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
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assign O = S1 ? (S0 ? I3 : I2)
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: (S0 ? I1 : I0);
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endmodule
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// Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
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// Necessary since RAMD* and SRL* have both combinatorial (i.e.
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// same-cycle read operation) and sequential (write operation
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// is only committed on the next clock edge).
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// To model the combinatorial path, such cells have to be split
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// into comb and seq parts, with this box modelling only the former.
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(* abc9_box_id=2000 *)
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module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
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endmodule
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// Box to emulate comb/seq behaviour of RAMD128
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(* abc9_box_id=2001 *)
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module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
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endmodule
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// Modules used to model the comb/seq behaviour of DSP48E1
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// With abc9_map.v responsible for splicing the below modules
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// between the combinatorial DSP48E1 box (e.g. disconnecting
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// A when AREG, MREG or PREG is enabled and splicing in the
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// "$__ABC9_DSP48E1_REG" blackbox as "REG" in the diagram below)
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// this acts to first disables the combinatorial path (as there
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// is no connectivity through REG), and secondly, since this is
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// blackbox a new PI will be introduced with an arrival time of
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// zero.
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// Note: Since these "$__ABC9_DSP48E1_REG" modules are of a
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// sequential nature, they are not passed as a box to ABC and
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// (desirably) represented as PO/PIs.
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//
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// At the DSP output, we place a blackbox mux ("M" in the diagram
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// below) to capture the fact that the critical-path could come
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// from any one of its inputs.
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// In contrast to "REG", the "$__ABC9_DSP48E1_*_MUX" modules are
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// combinatorial blackboxes that do get passed to ABC.
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// The propagation delay through this box (specified in the box
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// file) captures the arrival time of the register (i.e.
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// propagation from AREG to P after clock edge), or zero delay
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// for the combinatorial path from the DSP.
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//
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// Doing so should means that ABC is able to analyse the
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// worst-case delay through to P, regardless of if it was
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// through any combinatorial paths (e.g. B, below) or an
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// internal register (A2REG).
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// However, the true value of being as complete as this is
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// questionable since if AREG=1 and BREG=0 (as below)
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// then the worse-case path would very likely be through B
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// and very unlikely to be through AREG.Q...?
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//
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// In graphical form:
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//
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// +-----+
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// +------>> REG >>----+
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// | +-----+ |
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// | |
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// | +---------+ | __
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// A >>-+X X-| | +--| \
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// | DSP48E1 |P | M |--->> P
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// | AREG=1 |-------|__/
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// B >>------| |
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// +---------+
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//
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`define ABC9_DSP48E1_MUX(__NAME__) """
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module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O);
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endmodule
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"""
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(* abc9_box_id=2100 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_P_MUX )
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(* abc9_box_id=2101 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_PCOUT_MUX )
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(* abc9_box_id=2102 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_P_MUX )
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(* abc9_box_id=2103 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_MULT_DPORT_PCOUT_MUX )
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(* abc9_box_id=2104 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_P_MUX )
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(* abc9_box_id=2105 *) `ABC9_DSP48E1_MUX(\$__ABC9_DSP48E1_PCOUT_MUX )
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`define ABC9_DSP48E1(__NAME__) """
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module __NAME__ (
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output [29:0] ACOUT,
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output [17:0] BCOUT,
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output reg CARRYCASCOUT,
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output reg [3:0] CARRYOUT,
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output reg MULTSIGNOUT,
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output OVERFLOW,
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output reg signed [47:0] P,
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output PATTERNBDETECT,
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output PATTERNDETECT,
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output [47:0] PCOUT,
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output UNDERFLOW,
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input signed [29:0] A,
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input [29:0] ACIN,
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input [3:0] ALUMODE,
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input signed [17:0] B,
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input [17:0] BCIN,
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input [47:0] C,
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input CARRYCASCIN,
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input CARRYIN,
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input [2:0] CARRYINSEL,
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input CEA1,
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input CEA2,
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input CEAD,
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input CEALUMODE,
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input CEB1,
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input CEB2,
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input CEC,
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input CECARRYIN,
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input CECTRL,
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input CED,
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input CEINMODE,
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input CEM,
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input CEP,
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input CLK,
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input [24:0] D,
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input [4:0] INMODE,
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input MULTSIGNIN,
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input [6:0] OPMODE,
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input [47:0] PCIN,
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input RSTA,
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input RSTALLCARRYIN,
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input RSTALUMODE,
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input RSTB,
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input RSTC,
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input RSTCTRL,
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input RSTD,
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input RSTINMODE,
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input RSTM,
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input RSTP
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);
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parameter integer ACASCREG = 1;
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parameter integer ADREG = 1;
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parameter integer ALUMODEREG = 1;
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parameter integer AREG = 1;
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parameter AUTORESET_PATDET = "NO_RESET";
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parameter A_INPUT = "DIRECT";
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parameter integer BCASCREG = 1;
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parameter integer BREG = 1;
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parameter B_INPUT = "DIRECT";
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parameter integer CARRYINREG = 1;
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parameter integer CARRYINSELREG = 1;
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parameter integer CREG = 1;
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parameter integer DREG = 1;
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parameter integer INMODEREG = 1;
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parameter integer MREG = 1;
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parameter integer OPMODEREG = 1;
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parameter integer PREG = 1;
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parameter SEL_MASK = "MASK";
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parameter SEL_PATTERN = "PATTERN";
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parameter USE_DPORT = "FALSE";
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parameter USE_MULT = "MULTIPLY";
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parameter USE_PATTERN_DETECT = "NO_PATDET";
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parameter USE_SIMD = "ONE48";
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parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
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parameter [47:0] PATTERN = 48'h000000000000;
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parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
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parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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parameter [4:0] IS_INMODE_INVERTED = 5'b0;
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parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
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endmodule
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"""
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(* abc9_box_id=3000 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT )
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(* abc9_box_id=3001 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1_MULT_DPORT )
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(* abc9_box_id=3002 *) `ABC9_DSP48E1(\$__ABC9_DSP48E1 )
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