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Rename abc_* names/attributes to more precisely be abc9_*

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This commit is contained in:
Eddie Hung 2019-10-04 11:04:10 -07:00
parent 9fef1df3c1
commit aae2b9fd9c
34 changed files with 313 additions and 305 deletions
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4
techlibs/ice40/synth_ice40.cc
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@ -349,7 +349,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc == "abc9") {
run("read_verilog -icells -lib +/ice40/abc_model.v");
run("read_verilog -icells -lib +/ice40/abc9_model.v");
int wire_delay;
if (device_opt == "lp")
wire_delay = 400;
@ -357,7 +357,7 @@ struct SynthIce40Pass : public ScriptPass
wire_delay = 750;
else
wire_delay = 250;
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
run(abc + stringf(" -W %d -lut +/ice40/abc9_%s.lut -box +/ice40/abc9_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
}
else
run(abc + " -dress -lut 4", "(skip if -noabc)");