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https://github.com/YosysHQ/yosys
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Rename abc_* names/attributes to more precisely be abc9_*
This commit is contained in:
Eddie Hung
parent
9fef1df3c1
commit
aae2b9fd9c
34 changed files with 313 additions and 305 deletions
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@ -2,9 +2,9 @@
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`define SB_DFF_REG reg Q = 0
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// `define SB_DFF_REG reg Q
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`define ABC_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc_arrival=TIME *) `endif
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`define ABC_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc_arrival=TIME *) `endif
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`define ABC_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc_arrival=TIME *) `endif
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`define ABC9_ARRIVAL_HX(TIME) `ifdef ICE40_HX (* abc9_arrival=TIME *) `endif
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`define ABC9_ARRIVAL_LP(TIME) `ifdef ICE40_LP (* abc9_arrival=TIME *) `endif
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`define ABC9_ARRIVAL_U(TIME) `ifdef ICE40_U (* abc9_arrival=TIME *) `endif
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// SiliconBlue IO Cells
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@ -152,9 +152,9 @@ endmodule
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// Positive Edge SiliconBlue FF Cells
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module SB_DFF (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, D
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);
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@ -163,9 +163,9 @@ module SB_DFF (
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endmodule
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module SB_DFFE (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, D
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);
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@ -175,9 +175,9 @@ module SB_DFFE (
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endmodule
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module SB_DFFSR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, R, D
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);
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@ -189,9 +189,9 @@ module SB_DFFSR (
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endmodule
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module SB_DFFR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, R, D
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);
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@ -203,9 +203,9 @@ module SB_DFFR (
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endmodule
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module SB_DFFSS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, S, D
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);
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@ -217,9 +217,9 @@ module SB_DFFSS (
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endmodule
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module SB_DFFS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, S, D
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);
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@ -231,9 +231,9 @@ module SB_DFFS (
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endmodule
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module SB_DFFESR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, R, D
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);
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@ -247,9 +247,9 @@ module SB_DFFESR (
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endmodule
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module SB_DFFER (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, R, D
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);
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@ -261,9 +261,9 @@ module SB_DFFER (
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endmodule
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module SB_DFFESS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, S, D
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);
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@ -277,9 +277,9 @@ module SB_DFFESS (
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endmodule
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module SB_DFFES (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, S, D
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);
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@ -293,9 +293,9 @@ endmodule
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// Negative Edge SiliconBlue FF Cells
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module SB_DFFN (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, D
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);
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@ -304,9 +304,9 @@ module SB_DFFN (
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endmodule
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module SB_DFFNE (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, D
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);
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@ -316,9 +316,9 @@ module SB_DFFNE (
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endmodule
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module SB_DFFNSR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, R, D
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);
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@ -330,9 +330,9 @@ module SB_DFFNSR (
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endmodule
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module SB_DFFNR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, R, D
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);
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@ -344,9 +344,9 @@ module SB_DFFNR (
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endmodule
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module SB_DFFNSS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, S, D
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);
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@ -358,9 +358,9 @@ module SB_DFFNSS (
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endmodule
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module SB_DFFNS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, S, D
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);
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@ -372,9 +372,9 @@ module SB_DFFNS (
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endmodule
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module SB_DFFNESR (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, R, D
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);
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@ -388,9 +388,9 @@ module SB_DFFNESR (
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endmodule
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module SB_DFFNER (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, R, D
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);
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@ -402,9 +402,9 @@ module SB_DFFNER (
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endmodule
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module SB_DFFNESS (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, S, D
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);
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@ -418,9 +418,9 @@ module SB_DFFNESS (
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endmodule
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module SB_DFFNES (
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output `SB_DFF_REG,
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input C, E, S, D
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);
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@ -434,9 +434,9 @@ endmodule
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// SiliconBlue RAM Cells
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module SB_RAM40_4K (
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`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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`ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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`ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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@ -605,9 +605,9 @@ module SB_RAM40_4K (
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endmodule
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module SB_RAM40_4KNR (
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`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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`ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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`ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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output [15:0] RDATA,
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input RCLKN, RCLKE, RE,
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input [10:0] RADDR,
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@ -673,9 +673,9 @@ module SB_RAM40_4KNR (
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endmodule
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module SB_RAM40_4KNW (
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`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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`ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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`ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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output [15:0] RDATA,
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input RCLK, RCLKE, RE,
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input [10:0] RADDR,
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@ -741,9 +741,9 @@ module SB_RAM40_4KNW (
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endmodule
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module SB_RAM40_4KNRNW (
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`ABC_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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`ABC_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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`ABC9_ARRIVAL_HX(2146) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401
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`ABC9_ARRIVAL_LP(3163) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401
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`ABC9_ARRIVAL_U(1179) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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output [15:0] RDATA,
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input RCLKN, RCLKE, RE,
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input [10:0] RADDR,
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@ -813,9 +813,9 @@ endmodule
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module ICESTORM_LC (
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input I0, I1, I2, I3, CIN, CLK, CEN, SR,
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output LO,
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`ABC_ARRIVAL_HX(540)
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`ABC_ARRIVAL_LP(796)
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`ABC_ARRIVAL_U(1391)
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`ABC9_ARRIVAL_HX(540)
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`ABC9_ARRIVAL_LP(796)
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`ABC9_ARRIVAL_U(1391)
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output O,
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output COUT
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);
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@ -1417,7 +1417,6 @@ module SB_MAC16 (
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input ADDSUBTOP, ADDSUBBOT,
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input OHOLDTOP, OHOLDBOT,
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input CI, ACCUMCI, SIGNEXTIN,
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//`ABC_ARRIVAL_U(1984) // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026
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output [31:0] O,
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output CO, ACCUMCO, SIGNEXTOUT
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);
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