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Merge pull request #139 from azonenberg/master

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Add GreenPak4 LF oscillator support, renamed internal cell for consistency
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Clifford Wolf 2016-03-28 16:53:24 +02:00
commit aade2c21fa
1 changed files with 44 additions and 2 deletions
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46
techlibs/greenpak4/cells_sim.v
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@ -55,10 +55,52 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
module GP4_VDD(output OUT);
module GP_VDD(output OUT);
assign OUT = 1;
endmodule
module GP4_VSS(output OUT);
module GP_VSS(output OUT);
assign OUT = 0;
endmodule
module GP_LFOSC(input PWRDN, output reg CLKOUT);
parameter PWRDN_EN = 0;
parameter AUTO_PWRDN = 0;
parameter OUT_DIV = 1;
initial CLKOUT = 0;
always begin
if(PWRDN)
clkout = 0;
else begin
//half period of 1730 Hz
#289017;
clkout = ~clkout;
end
end
endmodule
module GP_COUNT8(input CLK, input wire RST, output reg OUT);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
//more complex hard IP blocks are not supported for simulation yet
endmodule
module GP_COUNT14(input CLK, input wire RST, output reg OUT);
parameter RESET_MODE = "RISING";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
//more complex hard IP blocks are not supported for simulation yet
endmodule