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https://github.com/YosysHQ/yosys
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aigmap fix prefix
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parent
cb1640b873
commit
aad94abef4
1 changed files with 6 additions and 6 deletions
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@ -108,8 +108,8 @@ struct AigmapPass : public Pass {
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SigBit A = sigs.at(node.left_parent);
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SigBit A = sigs.at(node.left_parent);
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SigBit B = sigs.at(node.right_parent);
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SigBit B = sigs.at(node.right_parent);
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if (nand_mode && node.inverter) {
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if (nand_mode && node.inverter) {
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bit = module->addWire(NEW_ID);
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bit = module->addWire(NEW_ID2_SUFFIX("bit"));
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auto gate = module->addNandGate(NEW_ID, A, B, bit);
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auto gate = module->addNandGate(NEW_ID2_SUFFIX("nand"), A, B, bit);
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if (select_mode)
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if (select_mode)
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new_sel.insert(gate->name);
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new_sel.insert(gate->name);
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@ -119,8 +119,8 @@ struct AigmapPass : public Pass {
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if (and_cache.count(key))
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if (and_cache.count(key))
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bit = and_cache.at(key);
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bit = and_cache.at(key);
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else {
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else {
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bit = module->addWire(NEW_ID);
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bit = module->addWire(NEW_ID2_SUFFIX("bit"));
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auto gate = module->addAndGate(NEW_ID, A, B, bit);
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auto gate = module->addAndGate(NEW_ID2_SUFFIX("and"), A, B, bit);
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if (select_mode)
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if (select_mode)
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new_sel.insert(gate->name);
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new_sel.insert(gate->name);
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}
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}
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@ -128,8 +128,8 @@ struct AigmapPass : public Pass {
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}
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}
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if (node.inverter) {
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if (node.inverter) {
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SigBit new_bit = module->addWire(NEW_ID);
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SigBit new_bit = module->addWire(NEW_ID2_SUFFIX("new_bit"));
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auto gate = module->addNotGate(NEW_ID, bit, new_bit);
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auto gate = module->addNotGate(NEW_ID2_SUFFIX("inv"), bit, new_bit);
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bit = new_bit;
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bit = new_bit;
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if (select_mode)
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if (select_mode)
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new_sel.insert(gate->name);
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new_sel.insert(gate->name);
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