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aigmap fix prefix

This commit is contained in:
Akash Levy 2024-11-16 21:58:11 -08:00
parent cb1640b873
commit aad94abef4

View file

@ -108,8 +108,8 @@ struct AigmapPass : public Pass {
SigBit A = sigs.at(node.left_parent); SigBit A = sigs.at(node.left_parent);
SigBit B = sigs.at(node.right_parent); SigBit B = sigs.at(node.right_parent);
if (nand_mode && node.inverter) { if (nand_mode && node.inverter) {
bit = module->addWire(NEW_ID); bit = module->addWire(NEW_ID2_SUFFIX("bit"));
auto gate = module->addNandGate(NEW_ID, A, B, bit); auto gate = module->addNandGate(NEW_ID2_SUFFIX("nand"), A, B, bit);
if (select_mode) if (select_mode)
new_sel.insert(gate->name); new_sel.insert(gate->name);
@ -119,8 +119,8 @@ struct AigmapPass : public Pass {
if (and_cache.count(key)) if (and_cache.count(key))
bit = and_cache.at(key); bit = and_cache.at(key);
else { else {
bit = module->addWire(NEW_ID); bit = module->addWire(NEW_ID2_SUFFIX("bit"));
auto gate = module->addAndGate(NEW_ID, A, B, bit); auto gate = module->addAndGate(NEW_ID2_SUFFIX("and"), A, B, bit);
if (select_mode) if (select_mode)
new_sel.insert(gate->name); new_sel.insert(gate->name);
} }
@ -128,8 +128,8 @@ struct AigmapPass : public Pass {
} }
if (node.inverter) { if (node.inverter) {
SigBit new_bit = module->addWire(NEW_ID); SigBit new_bit = module->addWire(NEW_ID2_SUFFIX("new_bit"));
auto gate = module->addNotGate(NEW_ID, bit, new_bit); auto gate = module->addNotGate(NEW_ID2_SUFFIX("inv"), bit, new_bit);
bit = new_bit; bit = new_bit;
if (select_mode) if (select_mode)
new_sel.insert(gate->name); new_sel.insert(gate->name);