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Rearrange command ordering and model checking
Now under the yosys flows section.
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Krystine Sherwin
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4 changed files with 379 additions and 385 deletions
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Flows, command types, and order
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-------------------------------
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===============================
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Synthesis granularity
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~~~~~~~~~~~~~~~~~~~~~
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Command order
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-------------
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Formal verification
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.. todo:: copypaste
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Intro to coarse-grain synthesis
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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In coarse-grain synthesis the target architecture has cells of the same
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complexity or larger complexity than the internal RTL representation.
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For example:
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.. code:: verilog
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wire [15:0] a, b;
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wire [31:0] c, y;
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assign y = a * b + c;
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This circuit contains two cells in the RTL representation: one multiplier and
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one adder. In some architectures this circuit can be implemented using
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a single circuit element, for example an FPGA DSP core. Coarse grain synthesis
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is this mapping of groups of circuit elements to larger components.
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Fine-grain synthesis would be matching the circuit elements to smaller
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components, such as LUTs, gates, or half- and full-adders.
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The extract pass
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~~~~~~~~~~~~~~~~
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- Like the :cmd:ref:`techmap` pass, the :cmd:ref:`extract` pass is called with a
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map file. It compares the circuits inside the modules of the map file with the
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design and looks for sub-circuits in the design that match any of the modules
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in the map file.
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- If a match is found, the :cmd:ref:`extract` pass will replace the matching
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subcircuit with an instance of the module from the map file.
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- In a way the :cmd:ref:`extract` pass is the inverse of the techmap pass.
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.. todo:: copypaste
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00a.*
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:class: width-helper
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before `extract`
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_00b.*
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:class: width-helper
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after `extract`
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_xmap.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_xmap.v``
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.. code:: yoscrypt
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read_verilog macc_simple_test.v
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hierarchy -check -top test
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extract -map macc_simple_xmap.v;;
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test_01.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_01.v``
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_01a.*
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:class: width-helper
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_01b.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test_02.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_02.v``
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_02a.*
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:class: width-helper
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_simple_test_02b.*
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:class: width-helper
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The wrap-extract-unwrap method
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Often a coarse-grain element has a constant bit-width, but can be used to
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implement operations with a smaller bit-width. For example, a 18x25-bit multiplier
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can also be used to implement 16x20-bit multiplication.
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A way of mapping such elements in coarse grain synthesis is the wrap-extract-unwrap method:
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wrap
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Identify candidate-cells in the circuit and wrap them in a cell with a
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constant wider bit-width using :cmd:ref:`techmap`. The wrappers use the same
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parameters as the original cell, so the information about the original width
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of the ports is preserved. Then use the ``connwrappers`` command to connect up
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the bit-extended in- and outputs of the wrapper cells.
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extract
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Now all operations are encoded using the same bit-width as the coarse grain
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element. The :cmd:ref:`extract` command can be used to replace circuits with
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cells of the target architecture.
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unwrap
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The remaining wrapper cell can be unwrapped using :cmd:ref:`techmap`.
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Example: DSP48_MACC
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~~~~~~~~~~~~~~~~~~~
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This section details an example that shows how to map MACC operations of
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arbitrary size to MACC cells with a 18x25-bit multiplier and a 48-bit adder
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(such as the Xilinx DSP48 cells).
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Preconditioning: ``macc_xilinx_swap_map.v``
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Make sure ``A`` is the smaller port on all multipliers
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.. todo:: copypaste
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v``
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Wrapping multipliers: ``macc_xilinx_wrap_map.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
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:language: verilog
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:lines: 1-46
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v``
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Wrapping adders: ``macc_xilinx_wrap_map.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
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:language: verilog
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:lines: 48-89
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v``
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Extract: ``macc_xilinx_xmap.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_xmap.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_xmap.v``
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... simply use the same wrapping commands on this module as on the design to
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create a template for the :cmd:ref:`extract` command.
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Unwrapping multipliers: ``macc_xilinx_unwrap_map.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
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:language: verilog
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:lines: 1-30
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v``
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Unwrapping adders: ``macc_xilinx_unwrap_map.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
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:language: verilog
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:lines: 32-61
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:caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_test.v
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:language: verilog
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:lines: 1-6
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:caption: ``test1`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v``
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1a.*
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:class: width-helper
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.*
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:class: width-helper
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.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_test.v
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:language: verilog
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:lines: 8-13
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:caption: ``test2`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v``
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2a.*
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:class: width-helper
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.*
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:class: width-helper
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Wrapping in ``test1``:
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.*
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:class: width-helper
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.. code:: yoscrypt
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper \
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Y Y_WIDTH \
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-unsigned $__add_wrapper \
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Y Y_WIDTH ;;
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.*
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:class: width-helper
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Wrapping in ``test2``:
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2b.*
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:class: width-helper
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.. code:: yoscrypt
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techmap -map macc_xilinx_wrap_map.v
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connwrappers -unsigned $__mul_wrapper \
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Y Y_WIDTH \
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-unsigned $__add_wrapper \
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Y Y_WIDTH ;;
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.*
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:class: width-helper
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Extract in ``test1``:
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.. code:: yoscrypt
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design -push
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read_verilog macc_xilinx_xmap.v
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techmap -map macc_xilinx_swap_map.v
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techmap -map macc_xilinx_wrap_map.v;;
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design -save __macc_xilinx_xmap
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design -pop
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extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1c.*
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:class: width-helper
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test1d.*
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:class: width-helper
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Extract in ``test2``:
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.. code:: yoscrypt
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design -push
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read_verilog macc_xilinx_xmap.v
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techmap -map macc_xilinx_swap_map.v
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techmap -map macc_xilinx_wrap_map.v;;
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design -save __macc_xilinx_xmap
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design -pop
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extract -constports -ignore_parameters \
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-map %__macc_xilinx_xmap \
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-swap $__add_wrapper A,B ;;
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2c.*
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:class: width-helper
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.*
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:class: width-helper
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Unwrap in ``test2``:
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2d.*
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:class: width-helper
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.. figure:: ../../images/res/PRESENTATION_ExAdv/macc_xilinx_test2e.*
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:class: width-helper
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.. code:: yoscrypt
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techmap -map macc_xilinx_unwrap_map.v ;;
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Symbolic model checking
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-----------------------
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.. todo:: copypaste
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.. note::
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While it is possible to perform model checking directly in Yosys, it
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is highly recommended to use SBY or EQY for formal hardware verification.
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Symbolic Model Checking (SMC) is used to formally prove that a circuit has (or
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has not) a given property.
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One application is Formal Equivalence Checking: Proving that two circuits are
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identical. For example this is a very useful feature when debugging custom
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passes in Yosys.
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Other applications include checking if a module conforms to interface standards.
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The :cmd:ref:`sat` command in Yosys can be used to perform Symbolic Model
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Checking.
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Checking techmap
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~~~~~~~~~~~~~~~~
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Remember the following example from :doc:`/getting_started/typical_phases`?
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01_map.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.ys
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:language: yoscrypt
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:caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.ys``
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Lets see if it is correct..
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.. code:: yoscrypt
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# read test design
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read_verilog techmap_01.v
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hierarchy -top test
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# create two version of the design: test_orig and test_mapped
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copy test test_orig
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rename test test_mapped
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# apply the techmap only to test_mapped
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techmap -map techmap_01_map.v test_mapped
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# create a miter circuit to test equivalence
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miter -equiv -make_assert -make_outputs test_orig test_mapped miter
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flatten miter
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# run equivalence check
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sat -verify -prove-asserts -show-inputs -show-outputs miter
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Result:
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.. code::
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Solving problem with 945 variables and 2505 clauses..
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SAT proof finished - no model found: SUCCESS!
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AXI4 Stream Master
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~~~~~~~~~~~~~~~~~~
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The following AXI4 Stream Master has a bug. But the bug is not exposed if the
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slave keeps ``tready`` asserted all the time. (Something a test bench might do.)
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Symbolic Model Checking can be used to expose the bug and find a sequence of
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values for ``tready`` that yield the incorrect behavior.
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.. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_master.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExOth/axis_master.v``
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.. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_test.v
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:language: verilog
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:caption: ``docs/resources/PRESENTATION_ExOth/axis_test.v``
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.. code:: yoscrypt
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read_verilog -sv axis_master.v axis_test.v
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hierarchy -top axis_test
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proc; flatten;;
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sat -seq 50 -prove-asserts
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Result with unmodified ``axis_master.v``:
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.. code::
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Solving problem with 159344 variables and 442126 clauses..
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SAT proof finished - model found: FAIL!
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Result with fixed ``axis_master.v``:
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.. code::
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Solving problem with 159144 variables and 441626 clauses..
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SAT proof finished - no model found: SUCCESS!
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