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-module_name arg to go before -clk_name

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This commit is contained in:
Eddie Hung 2019-02-08 12:49:55 -08:00
parent 587872236e
commit aa66d8f12f
1 changed files with 7 additions and 7 deletions
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14
frontends/aiger/aigerparse.cc
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@ -363,13 +363,13 @@ struct AigerFrontend : public Frontend {
log(" read_aiger [options] [filename]\n"); log(" read_aiger [options] [filename]\n");
log("\n"); log("\n");
log("Load module from an AIGER file into the current design.\n"); log("Load module from an AIGER file into the current design.\n");
log("\n");
log(" -module_name <module_name>\n");
log(" Name of module to be created (default: <filename>)"
log("\n"); log("\n");
log(" -clk_name <wire_name>\n"); log(" -clk_name <wire_name>\n");
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of"); log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
log(" this name (default: clk)\n"); log(" this name (default: clk)\n");
log("\n");
log(" -module_name <module_name>\n");
log(" Name of module to be created (default: <filename>)"
#ifdef _WIN32 #ifdef _WIN32
"top" // FIXME "top" // FIXME
#else #else
@ -388,14 +388,14 @@ struct AigerFrontend : public Frontend {
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx]; std::string arg = args[argidx];
if (arg == "-clk_name" && argidx+1 < args.size()) {
clk_name = RTLIL::escape_id(args[++argidx]);
continue;
}
if (arg == "-module_name" && argidx+1 < args.size()) { if (arg == "-module_name" && argidx+1 < args.size()) {
module_name = RTLIL::escape_id(args[++argidx]); module_name = RTLIL::escape_id(args[++argidx]);
continue; continue;
} }
if (arg == "-clk_name" && argidx+1 < args.size()) {
clk_name = RTLIL::escape_id(args[++argidx]);
continue;
}
break; break;
} }
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);