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https://github.com/YosysHQ/yosys
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working splinets
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parent
0d854120a7
commit
aa4c5e9ee5
1 changed files with 24 additions and 5 deletions
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@ -328,6 +328,15 @@ void calculateFanout(RTLIL::Module *module, SigMap &sigmap, dict<RTLIL::SigSpec,
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}
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}
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std::string substringUntil(const std::string& str, char delimiter) {
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size_t pos = str.find(delimiter);
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if (pos != std::string::npos) {
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return str.substr(0, pos);
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} else {
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return str;
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}
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}
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struct AnnotateCellFanout : public ScriptPass {
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AnnotateCellFanout() : ScriptPass("annotate_cell_fanout", "Annotate the cell fanout on the cell") {}
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void script() override {}
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@ -372,8 +381,9 @@ struct AnnotateCellFanout : public ScriptPass {
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cellsToFixFanout.push_back(cell);
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}
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}
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std::set<std::string> netsToSplitS;
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std::string netsToSplit;
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std::string portsToSplit;
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for (Cell* cell : cellsToFixFanout) {
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RTLIL::SigSpec cellOutSig;
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for (auto &conn : cell->connections()) {
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@ -384,11 +394,20 @@ struct AnnotateCellFanout : public ScriptPass {
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break;
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}
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}
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netsToSplit += std::string(" w:") + getParentWire(cellOutSig)->name.c_str();
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netsToSplit += std::string(" x:") + getParentWire(cellOutSig)->name.c_str();
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std::string parent = getParentWire(cellOutSig)->name.c_str();
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parent = substringUntil(parent, '[');
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if (netsToSplitS.find(parent) == netsToSplitS.end()) {
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netsToSplit += std::string(" w:") + parent; // Wire
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portsToSplit += std::string(" o:") + parent; // Port
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netsToSplitS.insert(parent);
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std::string splitnets = std::string("splitnets ") + netsToSplit;
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Pass::call(design, splitnets);
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splitnets = std::string("splitnets -ports_only ") + portsToSplit;
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Pass::call(design, splitnets);
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netsToSplit = "";
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portsToSplit = "";
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}
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}
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std::string splitnets = std::string("splitnets ") + netsToSplit;
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Pass::call(design, splitnets);
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}
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{
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