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Merge pull request #185 from Silimate/opt_priority_onehot
opt_priority_onehot
This commit is contained in:
Akash Levy
GitHub
commit
aa3ebe430e
4 changed files with 1365 additions and 0 deletions
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@ -29,6 +29,7 @@ OBJS += passes/opt/opt_argmax.o
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OBJS += passes/opt/opt_balance_tree.o
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OBJS += passes/opt/opt_parallel_prefix.o
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OBJS += passes/opt/opt_prienc.o
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OBJS += passes/opt/opt_priority_onehot.o
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OBJS += passes/opt/peepopt.o
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GENFILES += passes/opt/peepopt_pm.h
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828
passes/opt/opt_priority_onehot.cc
Normal file
828
passes/opt/opt_priority_onehot.cc
Normal file
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@ -0,0 +1,828 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2026 Akash Levy <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include <algorithm>
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#include <cctype>
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#include <map>
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#include <queue>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static int clog2_int(int x)
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{
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int r = 0;
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while ((1 << r) < x)
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r++;
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return r;
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}
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static bool is_power_of_two(int x)
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{
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return x > 0 && (x & (x - 1)) == 0;
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}
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// Pack a per-lane integer vector into a Const with elem_w bits per lane.
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static Const pack_lanes(const vector<int> &vals, int elem_w)
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{
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vector<State> bits(vals.size() * elem_w, State::S0);
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for (int k = 0; k < GetSize(vals); k++)
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for (int b = 0; b < elem_w && b < 31; b++)
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if ((vals[k] >> b) & 1)
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bits[k * elem_w + b] = State::S1;
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return Const(bits);
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}
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struct OptPriorityOnehotWorker {
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// One detected priority-onehot region ready to be rewritten.
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struct Candidate {
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Wire *out_wire = nullptr; // one-hot output O (width W = 2^idx_w)
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Wire *valid_wire = nullptr; // request / valid bus V (width N)
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SigSpec valid_sig; // N bits
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SigSpec field_sig; // N * idx_w bits: concatenated per-lane index fields
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std::string index_name;
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int n = 0; // number of lanes
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int w = 0; // output width (power of two)
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int idx_w = 0; // clog2(w) == per-lane field width
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bool msb_first = false; // priority direction (false: lowest index wins)
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Cell *anchor = nullptr; // a driver cell of O, used for naming/src
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};
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struct TestVector {
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vector<int> valid;
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vector<int> field;
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};
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Module *module;
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SigMap sigmap;
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dict<SigBit, Cell *> bit_to_driver;
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pool<SigBit> input_port_bits;
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Cell *cell = nullptr;
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int min_width = 4;
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int max_width = 64;
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int regions_rewritten = 0;
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int cells_added = 0;
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OptPriorityOnehotWorker(Module *module) : module(module), sigmap(module)
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{
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build_indexes();
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}
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bool is_sequential(Cell *c)
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{
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return c->type.in(
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ID($ff), ID($dff), ID($dffe), ID($adff), ID($adffe),
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ID($sdff), ID($sdffe), ID($sdffce), ID($dffsr), ID($dffsre),
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ID($_DFF_P_), ID($_DFF_N_),
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ID($_DFFE_PP_), ID($_DFFE_PN_), ID($_DFFE_NP_), ID($_DFFE_NN_),
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ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
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ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_NN0_), ID($_DFF_NN1_),
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ID($dlatch), ID($adlatch), ID($dlatchsr),
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ID($mem), ID($mem_v2), ID($meminit), ID($meminit_v2),
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ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2),
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ID($fsm),
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ID($assert), ID($assume), ID($cover), ID($live), ID($fair),
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ID($print), ID($check),
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ID($anyconst), ID($anyseq), ID($allconst), ID($allseq),
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ID($initstate));
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}
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void build_indexes()
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{
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for (auto c : module->cells()) {
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if (is_sequential(c))
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continue;
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for (auto &conn : c->connections()) {
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if (!c->output(conn.first))
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continue;
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for (auto bit : sigmap(conn.second)) {
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if (!bit.wire)
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continue;
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auto it = bit_to_driver.find(bit);
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if (it == bit_to_driver.end())
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bit_to_driver[bit] = c;
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else if (it->second != c)
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it->second = nullptr;
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}
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}
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}
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for (auto w : module->wires()) {
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if (!w->port_input)
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continue;
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for (auto bit : sigmap(SigSpec(w)))
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if (bit.wire)
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input_port_bits.insert(bit);
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}
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}
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// Combinational fanin cone of `from`. Leaves are port-input bits or bits
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// driven by sequential cells / undriven. Returns false if size limits are
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// exceeded.
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bool get_cone(SigSpec from, pool<Cell *> &cone_cells, pool<SigBit> &leaf_bits,
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int max_cone_cells, int max_leaf_bits)
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{
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pool<SigBit> visited;
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std::queue<SigBit> worklist;
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for (auto bit : sigmap(from)) {
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if (!bit.wire)
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continue;
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if (visited.insert(bit).second)
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worklist.push(bit);
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}
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while (!worklist.empty()) {
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SigBit bit = worklist.front();
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worklist.pop();
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if (input_port_bits.count(bit)) {
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leaf_bits.insert(bit);
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if (GetSize(leaf_bits) > max_leaf_bits)
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return false;
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continue;
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}
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Cell *drv = bit_to_driver.at(bit, nullptr);
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if (drv == nullptr) {
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leaf_bits.insert(bit);
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if (GetSize(leaf_bits) > max_leaf_bits)
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return false;
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continue;
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}
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if (!cone_cells.insert(drv).second)
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continue;
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if (GetSize(cone_cells) > max_cone_cells)
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return false;
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for (auto &conn : drv->connections()) {
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if (!drv->input(conn.first))
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continue;
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for (auto in_bit : sigmap(conn.second)) {
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if (!in_bit.wire)
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continue;
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if (visited.insert(in_bit).second)
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worklist.push(in_bit);
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}
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}
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}
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return true;
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}
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// Discover the per-lane index field within candidate bus `d_sig_in`. The bus
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// is viewed as `n` lanes of stride `s = width/n`; each lane must contribute
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// exactly `idx_w` contiguous bits to the cone at a common within-lane offset
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// (handles packed fields, where s == idx_w, and sub-fields like id[*][4:1]).
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// `d_sig_in` may be a single flat input wire or a concatenation of per-lane
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// split-port wires (see collect_split_input_buses).
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bool infer_field(const SigSpec &d_sig_in, int n, int idx_w, int s,
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const pool<SigBit> &leaf_bits, SigSpec &field_sig)
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{
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SigSpec d_sig = sigmap(d_sig_in);
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dict<SigBit, int> d_offset;
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for (int i = 0; i < GetSize(d_sig); i++)
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if (d_sig[i].wire)
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d_offset[d_sig[i]] = i;
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vector<std::set<int>> lane_used(n);
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for (auto lb : leaf_bits) {
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auto it = d_offset.find(lb);
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if (it == d_offset.end())
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continue;
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int off = it->second;
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lane_used[off / s].insert(off % s);
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}
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int field_lo = -1;
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for (int k = 0; k < n; k++) {
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auto &used = lane_used[k];
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if (GetSize(used) != idx_w)
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return false;
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int lo = *used.begin();
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int expect = lo;
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for (int v : used) {
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if (v != expect)
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return false;
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expect++;
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}
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if (lo + idx_w > s)
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return false;
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if (field_lo < 0)
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field_lo = lo;
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else if (field_lo != lo)
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return false;
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}
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if (field_lo < 0)
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return false;
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field_sig = SigSpec();
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for (int k = 0; k < n; k++)
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field_sig.append(d_sig.extract(k * s + field_lo, idx_w));
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return true;
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}
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bool leaves_are_candidate_inputs(const pool<SigBit> &leaf_bits, const SigSpec &valid_sig,
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const SigSpec &field_sig)
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{
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pool<SigBit> allowed;
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for (auto bit : sigmap(valid_sig))
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if (bit.wire)
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allowed.insert(bit);
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for (auto bit : sigmap(field_sig))
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if (bit.wire)
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allowed.insert(bit);
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for (auto bit : leaf_bits)
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if (!allowed.count(bit))
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return false;
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return true;
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}
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struct InputBus {
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SigSpec sig;
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std::string name;
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int entries = 0;
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int elem_width = 0;
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};
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// Parse a split-port name of the form "base[index]" (Verific lowers packed
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// multi-dimensional ports into per-lane wires named this way).
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bool parse_indexed_port_name(Wire *wire, std::string &base, int &index)
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{
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std::string name = wire->name.str();
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size_t rbrack = name.size();
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if (rbrack == 0 || name[rbrack - 1] != ']')
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return false;
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size_t lbrack = name.rfind('[');
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if (lbrack == std::string::npos || lbrack + 1 >= rbrack - 1)
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return false;
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for (size_t i = lbrack + 1; i < rbrack - 1; i++)
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if (!isdigit(name[i]))
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return false;
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base = name.substr(0, lbrack);
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index = atoi(name.substr(lbrack + 1, rbrack - lbrack - 2).c_str());
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return true;
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}
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// Group per-lane split-port wires into contiguous, equal-width buses. The
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// run may start at any base index (Verific lowers both [N-1:0] -> id[0..N-1]
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// and [N:1] -> id[1..N]); we only require consecutive indices and matching
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// widths. The resulting sig is the ascending-index concatenation, so lane k
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// is sig[k*elem_width ...] = the (base+k)-th port.
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vector<InputBus> collect_split_input_buses(const vector<Wire *> &inputs)
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{
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std::map<std::string, vector<std::pair<int, Wire *>>> groups;
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for (auto w : inputs) {
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std::string base;
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int index = -1;
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if (parse_indexed_port_name(w, base, index))
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groups[base].push_back({index, w});
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}
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vector<InputBus> buses;
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for (auto &it : groups) {
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auto entries = it.second;
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std::sort(entries.begin(), entries.end(),
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[](const std::pair<int, Wire *> &a, const std::pair<int, Wire *> &b) {
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return a.first < b.first;
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});
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if (entries.empty())
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continue;
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bool contiguous = true;
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int base_index = entries.front().first;
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int elem_width = GetSize(entries.front().second);
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for (int i = 0; i < GetSize(entries); i++) {
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if (entries[i].first != base_index + i ||
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GetSize(entries[i].second) != elem_width) {
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contiguous = false;
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break;
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}
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}
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if (!contiguous)
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continue;
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SigSpec sig;
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for (auto &entry : entries)
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sig.append(SigSpec(entry.second));
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buses.push_back({sig, it.first, GetSize(entries), elem_width});
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}
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return buses;
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}
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bool find_anchor_driver(Wire *out_wire, Cell *&anchor)
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{
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for (auto bit : sigmap(SigSpec(out_wire))) {
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Cell *drv = bit_to_driver.at(bit, nullptr);
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if (drv != nullptr) {
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anchor = drv;
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return true;
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}
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}
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return false;
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}
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vector<TestVector> make_test_vectors(int n, int w)
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{
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vector<TestVector> vs;
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auto base_field = [&](int mul, int add) {
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vector<int> f(n);
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for (int k = 0; k < n; k++)
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f[k] = ((k * mul + add) % w + w) % w;
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return f;
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};
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// All invalid: output must be all-zero.
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{
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TestVector t;
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t.valid.assign(n, 0);
|
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t.field = base_field(1, 0);
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vs.push_back(t);
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}
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// Single valid lane: exercises every lane's field routing.
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for (int k = 0; k < n; k++) {
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TestVector t;
|
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t.valid.assign(n, 0);
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t.valid[k] = 1;
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t.field = base_field(1, 0);
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t.field[k] = k % w;
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vs.push_back(t);
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TestVector t2;
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t2.valid = t.valid;
|
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t2.field = base_field(3, 1);
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vs.push_back(t2);
|
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}
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// All valid: distinguishes priority direction.
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{
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TestVector t;
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t.valid.assign(n, 1);
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t.field = base_field(1, 0);
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vs.push_back(t);
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}
|
||||
{
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TestVector t;
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t.valid.assign(n, 1);
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t.field = base_field(-1, w - 1);
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vs.push_back(t);
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}
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||||
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// Prefix masks valid[k..n-1]: lowest-index winner is k (LSB-first).
|
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for (int k = 0; k < n; k++) {
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TestVector t;
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t.valid.assign(n, 0);
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for (int j = k; j < n; j++)
|
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t.valid[j] = 1;
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t.field = base_field(5, 2);
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vs.push_back(t);
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}
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// Suffix masks valid[0..k]: highest-index winner is k (MSB-first).
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for (int k = 0; k < n; k++) {
|
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TestVector t;
|
||||
t.valid.assign(n, 0);
|
||||
for (int j = 0; j <= k; j++)
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t.valid[j] = 1;
|
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t.field = base_field(7, 3);
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vs.push_back(t);
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}
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||||
|
||||
// Pairs with distinct fields: rejects OR-of-all and wrong direction.
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for (int i = 0; i < n; i++)
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for (int j = i + 1; j < n && j < i + 3; j++) {
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TestVector t;
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t.valid.assign(n, 0);
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t.valid[i] = 1;
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t.valid[j] = 1;
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t.field = base_field(2, 0);
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t.field[i] = (i + 1) % w;
|
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t.field[j] = (j + 5) % w;
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vs.push_back(t);
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||||
}
|
||||
|
||||
// Pseudo-random coverage.
|
||||
uint64_t lfsr = 0x1234567089abcdefULL;
|
||||
for (int r = 0; r < 32; r++) {
|
||||
lfsr ^= lfsr << 13;
|
||||
lfsr ^= lfsr >> 7;
|
||||
lfsr ^= lfsr << 17;
|
||||
TestVector t;
|
||||
t.valid.resize(n);
|
||||
t.field.resize(n);
|
||||
for (int k = 0; k < n; k++)
|
||||
t.valid[k] = (lfsr >> (k % 64)) & 1;
|
||||
uint64_t f = lfsr * 2654435761ULL;
|
||||
for (int k = 0; k < n; k++)
|
||||
t.field[k] = (int)((f >> ((k * 3) % 60)) % (uint64_t)w);
|
||||
vs.push_back(t);
|
||||
}
|
||||
|
||||
return vs;
|
||||
}
|
||||
|
||||
int expected_winner(const vector<int> &valid, int n, bool msb_first)
|
||||
{
|
||||
if (!msb_first) {
|
||||
for (int k = 0; k < n; k++)
|
||||
if (valid[k])
|
||||
return k;
|
||||
} else {
|
||||
for (int k = n - 1; k >= 0; k--)
|
||||
if (valid[k])
|
||||
return k;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool fingerprint(const Candidate &cand, bool msb_first)
|
||||
{
|
||||
ConstEval ce(module);
|
||||
SigSpec out_sig = sigmap(SigSpec(cand.out_wire));
|
||||
SigSpec valid_sig = sigmap(cand.valid_sig);
|
||||
SigSpec field_sig = sigmap(cand.field_sig);
|
||||
|
||||
vector<TestVector> vectors = make_test_vectors(cand.n, cand.w);
|
||||
for (auto &tv : vectors) {
|
||||
ce.push();
|
||||
ce.set(valid_sig, pack_lanes(tv.valid, 1));
|
||||
ce.set(field_sig, pack_lanes(tv.field, cand.idx_w));
|
||||
|
||||
SigSpec out = out_sig;
|
||||
SigSpec undef;
|
||||
bool ok = ce.eval(out, undef);
|
||||
ce.pop();
|
||||
if (!ok || !out.is_fully_const())
|
||||
return false;
|
||||
|
||||
Const oc = out.as_const();
|
||||
int winner = expected_winner(tv.valid, cand.n, msb_first);
|
||||
for (int p = 0; p < cand.w; p++) {
|
||||
bool expect = (winner >= 0) && (p == (tv.field[winner] % cand.w));
|
||||
bool actual = (p < GetSize(oc)) && (oc[p] == State::S1);
|
||||
if (expect != actual)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool check_candidate(Candidate &cand, const pool<SigBit> &leaf_bits)
|
||||
{
|
||||
if (cand.n < min_width || cand.n > max_width)
|
||||
return false;
|
||||
if (!is_power_of_two(cand.w) || (1 << cand.idx_w) != cand.w)
|
||||
return false;
|
||||
if (!leaves_are_candidate_inputs(leaf_bits, cand.valid_sig, cand.field_sig)) {
|
||||
log_debug(" reject %s (valid=%s index=%s): cone leaves outside valid+field\n",
|
||||
log_id(cand.out_wire), log_id(cand.valid_wire), cand.index_name.c_str());
|
||||
return false;
|
||||
}
|
||||
if (!find_anchor_driver(cand.out_wire, cand.anchor))
|
||||
return false;
|
||||
if (fingerprint(cand, false)) {
|
||||
cand.msb_first = false;
|
||||
return true;
|
||||
}
|
||||
if (fingerprint(cand, true)) {
|
||||
cand.msb_first = true;
|
||||
return true;
|
||||
}
|
||||
log_debug(" reject %s (valid=%s index=%s): fingerprint mismatch (both directions)\n",
|
||||
log_id(cand.out_wire), log_id(cand.valid_wire), cand.index_name.c_str());
|
||||
return false;
|
||||
}
|
||||
|
||||
struct Record {
|
||||
SigBit valid;
|
||||
SigSpec index;
|
||||
};
|
||||
|
||||
// Priority merge of two records: the left (higher-priority) record wins
|
||||
// unless it is invalid.
|
||||
Record combine(Cell *anchor, const Record &lhs, const Record &rhs)
|
||||
{
|
||||
Cell *cell = anchor;
|
||||
SigBit lhs_invalid = module->Not(NEW_ID2_SUFFIX("prionehot_ninv"), SigSpec(lhs.valid))[0];
|
||||
cells_added++;
|
||||
SigBit take_rhs = module->And(NEW_ID2_SUFFIX("prionehot_take"),
|
||||
SigSpec(lhs_invalid), SigSpec(rhs.valid))[0];
|
||||
cells_added++;
|
||||
|
||||
Record out;
|
||||
out.valid = module->Or(NEW_ID2_SUFFIX("prionehot_orv"),
|
||||
SigSpec(lhs.valid), SigSpec(rhs.valid))[0];
|
||||
cells_added++;
|
||||
out.index = module->Mux(NEW_ID2_SUFFIX("prionehot_mux"), lhs.index, rhs.index,
|
||||
SigSpec(take_rhs));
|
||||
cells_added++;
|
||||
return out;
|
||||
}
|
||||
|
||||
Record emit_tree_rec(Cell *anchor, const vector<Record> &leaves, int begin, int end)
|
||||
{
|
||||
log_assert(begin < end);
|
||||
if (begin + 1 == end)
|
||||
return leaves[begin];
|
||||
int mid = begin + (end - begin) / 2;
|
||||
Record lhs = emit_tree_rec(anchor, leaves, begin, mid);
|
||||
Record rhs = emit_tree_rec(anchor, leaves, mid, end);
|
||||
return combine(anchor, lhs, rhs);
|
||||
}
|
||||
|
||||
// Log-depth binary decoder gated by `valid`: returns a w-bit one-hot where
|
||||
// bit p is set iff valid && index == p.
|
||||
SigSpec emit_decode(Cell *anchor, SigSpec index, SigBit valid, int w, int idx_w)
|
||||
{
|
||||
Cell *cell = anchor;
|
||||
vector<SigBit> cur;
|
||||
cur.push_back(valid);
|
||||
for (int b = 0; b < idx_w; b++) {
|
||||
SigSpec idx_bit(index[b]);
|
||||
SigBit idx_bit_n = module->Not(NEW_ID2_SUFFIX("prionehot_ndec"), idx_bit)[0];
|
||||
cells_added++;
|
||||
int group = GetSize(cur);
|
||||
vector<SigBit> nxt(group * 2);
|
||||
for (int g = 0; g < group; g++) {
|
||||
nxt[g] = module->And(NEW_ID2_SUFFIX("prionehot_dec0"),
|
||||
SigSpec(cur[g]), SigSpec(idx_bit_n))[0];
|
||||
cells_added++;
|
||||
nxt[g + group] = module->And(NEW_ID2_SUFFIX("prionehot_dec1"),
|
||||
SigSpec(cur[g]), idx_bit)[0];
|
||||
cells_added++;
|
||||
}
|
||||
cur = std::move(nxt);
|
||||
}
|
||||
|
||||
SigSpec out;
|
||||
for (int p = 0; p < w; p++)
|
||||
out.append(cur[p]);
|
||||
return out;
|
||||
}
|
||||
|
||||
SigSpec emit_priority_onehot(const Candidate &cand)
|
||||
{
|
||||
vector<Record> leaves;
|
||||
for (int k = 0; k < cand.n; k++) {
|
||||
// Leftmost leaf has the highest priority.
|
||||
int lane = cand.msb_first ? (cand.n - 1 - k) : k;
|
||||
Record r;
|
||||
r.valid = cand.valid_sig[lane];
|
||||
r.index = cand.field_sig.extract(lane * cand.idx_w, cand.idx_w);
|
||||
leaves.push_back(r);
|
||||
}
|
||||
Record root = emit_tree_rec(cand.anchor, leaves, 0, GetSize(leaves));
|
||||
return emit_decode(cand.anchor, root.index, root.valid, cand.w, cand.idx_w);
|
||||
}
|
||||
|
||||
void disconnect_old_output(const Candidate &cand)
|
||||
{
|
||||
pool<SigBit> target_bits;
|
||||
for (auto bit : sigmap(SigSpec(cand.out_wire)))
|
||||
if (bit.wire)
|
||||
target_bits.insert(bit);
|
||||
|
||||
pool<Cell *> seen_cells;
|
||||
for (auto target : target_bits) {
|
||||
Cell *drv = bit_to_driver.at(target, nullptr);
|
||||
if (drv == nullptr || seen_cells.count(drv))
|
||||
continue;
|
||||
seen_cells.insert(drv);
|
||||
|
||||
for (auto &conn : drv->connections()) {
|
||||
if (!drv->output(conn.first))
|
||||
continue;
|
||||
SigSpec orig = conn.second;
|
||||
SigSpec replacement = orig;
|
||||
bool changed = false;
|
||||
Cell *cell = drv;
|
||||
Wire *dangling = module->addWire(NEW_ID2_SUFFIX("prionehot_dangling"),
|
||||
GetSize(orig));
|
||||
for (int i = 0; i < GetSize(orig); i++) {
|
||||
if (target_bits.count(sigmap(orig[i]))) {
|
||||
replacement[i] = SigBit(dangling, i);
|
||||
changed = true;
|
||||
}
|
||||
}
|
||||
if (changed)
|
||||
drv->setPort(conn.first, replacement);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void run()
|
||||
{
|
||||
if (module->has_processes_warn())
|
||||
return;
|
||||
|
||||
vector<Wire *> inputs;
|
||||
vector<Wire *> outputs;
|
||||
for (auto w : module->wires()) {
|
||||
if (w->port_input)
|
||||
inputs.push_back(w);
|
||||
if (w->port_output && !w->port_input)
|
||||
outputs.push_back(w);
|
||||
}
|
||||
|
||||
// Per-lane split-port buses ("id[0]".."id[N-1]") are grouped once.
|
||||
vector<InputBus> split_buses = collect_split_input_buses(inputs);
|
||||
|
||||
vector<Candidate> rewrites;
|
||||
pool<Wire *> claimed_outputs;
|
||||
for (auto out : outputs) {
|
||||
if (claimed_outputs.count(out))
|
||||
continue;
|
||||
int w = GetSize(out);
|
||||
if (w < 2 || !is_power_of_two(w))
|
||||
continue;
|
||||
int idx_w = clog2_int(w);
|
||||
|
||||
pool<Cell *> cone_cells;
|
||||
pool<SigBit> leaf_bits;
|
||||
int max_cone_cells = std::max(256, max_width * 96);
|
||||
int max_leaf_bits = max_width * max_width + max_width * w + max_width;
|
||||
if (!get_cone(SigSpec(out), cone_cells, leaf_bits, max_cone_cells, max_leaf_bits)) {
|
||||
log_debug("output %s (w=%d): cone exceeds size limits\n", log_id(out), w);
|
||||
continue;
|
||||
}
|
||||
if (cone_cells.empty())
|
||||
continue;
|
||||
log_debug("output %s (w=%d, idx_w=%d): cone %d cells, %d leaf bits\n",
|
||||
log_id(out), w, idx_w, GetSize(cone_cells), GetSize(leaf_bits));
|
||||
|
||||
bool done = false;
|
||||
for (auto valid : inputs) {
|
||||
if (done)
|
||||
break;
|
||||
int n = GetSize(valid);
|
||||
if (n < min_width || n > max_width)
|
||||
continue;
|
||||
|
||||
// Candidate index sources: a flat input bus split into n lanes,
|
||||
// or a per-lane split-port bus with n entries.
|
||||
vector<std::pair<SigSpec, std::string>> sources;
|
||||
for (auto d : inputs) {
|
||||
if (d == valid)
|
||||
continue;
|
||||
if (GetSize(d) % n == 0)
|
||||
sources.push_back({SigSpec(d), d->name.str()});
|
||||
}
|
||||
for (auto &bus : split_buses)
|
||||
if (bus.entries == n)
|
||||
sources.push_back({bus.sig, bus.name});
|
||||
|
||||
for (auto &src : sources) {
|
||||
int total = GetSize(src.first);
|
||||
if (total % n != 0)
|
||||
continue;
|
||||
int s = total / n;
|
||||
if (s < idx_w)
|
||||
continue;
|
||||
|
||||
SigSpec field_sig;
|
||||
if (!infer_field(src.first, n, idx_w, s, leaf_bits, field_sig)) {
|
||||
log_debug(" valid=%s index=%s (n=%d, s=%d): field layout inference failed\n",
|
||||
log_id(valid), src.second.c_str(), n, s);
|
||||
continue;
|
||||
}
|
||||
|
||||
Candidate cand;
|
||||
cand.out_wire = out;
|
||||
cand.valid_wire = valid;
|
||||
cand.valid_sig = SigSpec(valid);
|
||||
cand.field_sig = field_sig;
|
||||
cand.index_name = src.second;
|
||||
cand.n = n;
|
||||
cand.w = w;
|
||||
cand.idx_w = idx_w;
|
||||
if (!check_candidate(cand, leaf_bits))
|
||||
continue;
|
||||
|
||||
rewrites.push_back(cand);
|
||||
claimed_outputs.insert(out);
|
||||
log(" %s: %s <- priority_onehot(valid=%s, index=%s) "
|
||||
"[N=%d, W=%d, IDX_W=%d, %s]\n",
|
||||
log_id(module), log_id(out), log_id(valid), src.second.c_str(),
|
||||
cand.n, cand.w, cand.idx_w,
|
||||
cand.msb_first ? "MSB-first" : "LSB-first");
|
||||
done = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &cand : rewrites) {
|
||||
cell = cand.anchor;
|
||||
SigSpec new_out = emit_priority_onehot(cand);
|
||||
disconnect_old_output(cand);
|
||||
module->connect(SigSpec(cand.out_wire), new_out);
|
||||
regions_rewritten++;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
struct OptPriorityOnehotPass : public Pass {
|
||||
OptPriorityOnehotPass() : Pass("opt_priority_onehot",
|
||||
"rewrite priority-select + one-hot index scatter into balanced trees") {}
|
||||
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" opt_priority_onehot [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass uses functional fingerprinting to detect combinational regions\n");
|
||||
log("that compute a priority (first-set) select of a per-lane index field and\n");
|
||||
log("scatter the winning field into a one-hot output, regardless of how the\n");
|
||||
log("RTL was written (unrolled for-loops, leading-one chains, |= scatter, etc.).\n");
|
||||
log("\n");
|
||||
log("Concretely, for a request/valid bus of N lanes and a per-lane index field,\n");
|
||||
log("the region computes:\n");
|
||||
log("\n");
|
||||
log(" winner = first lane with valid[lane] set (lowest index by default)\n");
|
||||
log(" out = (winner exists) ? (1 << field[winner]) : 0\n");
|
||||
log("\n");
|
||||
log("where out has power-of-two width W = 2^idx_w and field is idx_w bits wide.\n");
|
||||
log("Each detected region is replaced with a balanced (log-depth) priority\n");
|
||||
log("selection tree feeding a log-depth one-hot decoder, replacing the\n");
|
||||
log("linear leading-one and scatter chains in the original RTL.\n");
|
||||
log("\n");
|
||||
log("The per-lane index field may be a sub-slice of a wider flat input bus\n");
|
||||
log("(e.g. id[*][4:1] of a packed [N][5] bus); the lane stride and field\n");
|
||||
log("offset are inferred from the fanin cone. Both LSB-first (lowest index\n");
|
||||
log("wins) and MSB-first priority directions are detected.\n");
|
||||
log("\n");
|
||||
log(" -max-width N, -max_width N\n");
|
||||
log(" maximum lane count to consider (default 64).\n");
|
||||
log("\n");
|
||||
log(" -min-width N, -min_width N\n");
|
||||
log(" minimum lane count to consider (default 4).\n");
|
||||
log("\n");
|
||||
log("After rewriting, the original cone cells become unused and are removed\n");
|
||||
log("by the trailing 'clean -purge'.\n");
|
||||
log("\n");
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing OPT_PRIORITY_ONEHOT pass (priority select + one-hot scatter).\n");
|
||||
|
||||
int max_width = 64;
|
||||
int min_width = 4;
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if ((args[argidx] == "-max-width" || args[argidx] == "-max_width") &&
|
||||
argidx + 1 < args.size()) {
|
||||
max_width = std::stoi(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
if ((args[argidx] == "-min-width" || args[argidx] == "-min_width") &&
|
||||
argidx + 1 < args.size()) {
|
||||
min_width = std::stoi(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
int total_regions = 0;
|
||||
int total_cells_added = 0;
|
||||
for (auto module : design->selected_modules()) {
|
||||
OptPriorityOnehotWorker worker(module);
|
||||
worker.max_width = max_width;
|
||||
worker.min_width = min_width;
|
||||
worker.run();
|
||||
total_regions += worker.regions_rewritten;
|
||||
total_cells_added += worker.cells_added;
|
||||
}
|
||||
|
||||
log("Rewrote %d region(s); emitted %d new cell(s).\n",
|
||||
total_regions, total_cells_added);
|
||||
|
||||
if (total_regions)
|
||||
Yosys::run_pass("clean -purge");
|
||||
}
|
||||
} OptPriorityOnehotPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
235
tests/silimate/opt_priority_onehot.sv
Normal file
235
tests/silimate/opt_priority_onehot.sv
Normal file
|
|
@ -0,0 +1,235 @@
|
|||
// Test designs for opt_priority_onehot.
|
||||
//
|
||||
// Each "positive" module computes a lowest/highest-index priority select of a
|
||||
// per-lane index field and scatters the winning field into a one-hot output,
|
||||
// mirroring the qor_spi_ra_binary_tree shape. The "negative" modules look
|
||||
// similar but compute a different function and must be left untouched.
|
||||
|
||||
// Main shape: N=16 lanes, 5-bit id lanes, 4-bit field id[*][4:1], LSB-first.
|
||||
module pri_onehot_basic (
|
||||
input wire [15:0] req,
|
||||
input wire [15:0][4:0] id,
|
||||
output reg [15:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [15:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 0; I < 16; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][4:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// One-based ports [N:1] / id[I][IDX_W:1], matching the qor_spi_ra_binary_tree
|
||||
// regression exactly (Verific splits id into id[1]..id[16]).
|
||||
module pri_onehot_onebased (
|
||||
input wire [16:1] req,
|
||||
input wire [16:1][4:0] id,
|
||||
output reg [15:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [16:1] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 1; I <= 16; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][4:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Packed field: no per-lane gap (ID_W == IDX_W == 4), field id[*][3:0].
|
||||
module pri_onehot_packed (
|
||||
input wire [15:0] req,
|
||||
input wire [15:0][3:0] id,
|
||||
output reg [15:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [15:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 0; I < 16; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][3:0]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Scaled down: N=8, 4-bit id lanes, 3-bit field id[*][3:1], W=8.
|
||||
module pri_onehot_w8 (
|
||||
input wire [7:0] req,
|
||||
input wire [7:0][3:0] id,
|
||||
output reg [7:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [7:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 0; I < 8; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][3:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Scaled up: N=32, 6-bit id lanes, 5-bit field id[*][5:1], W=32.
|
||||
module pri_onehot_w32 (
|
||||
input wire [31:0] req,
|
||||
input wire [31:0][5:0] id,
|
||||
output reg [31:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [31:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 0; I < 32; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][5:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Lane count != output width: N=8 lanes, 4-bit field, W=16.
|
||||
module pri_onehot_n8_w16 (
|
||||
input wire [7:0] req,
|
||||
input wire [7:0][4:0] id,
|
||||
output reg [15:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [7:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 0; I < 8; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][4:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// MSB-first priority: highest set index wins (W=8 to keep SAT cheap).
|
||||
module pri_onehot_msb (
|
||||
input wire [7:0] req,
|
||||
input wire [7:0][3:0] id,
|
||||
output reg [7:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [7:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 7; I >= 0; I--) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][3:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Two independent priority-onehot regions in one module.
|
||||
module pri_onehot_two_regions (
|
||||
input wire [7:0] req_a,
|
||||
input wire [7:0][3:0] id_a,
|
||||
input wire [7:0] req_b,
|
||||
input wire [7:0][3:0] id_b,
|
||||
output reg [7:0] oneh_a,
|
||||
output reg [7:0] oneh_b
|
||||
);
|
||||
always_comb begin
|
||||
reg [7:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh_a = '0;
|
||||
for (int I = 0; I < 8; I++) begin
|
||||
sel[I] = req_a[I] & ~(|acc);
|
||||
acc[I] = req_a[I];
|
||||
oneh_a[id_a[I][3:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
always_comb begin
|
||||
reg [7:0] acc2, sel2;
|
||||
acc2 = '0; sel2 = '0; oneh_b = '0;
|
||||
for (int I = 0; I < 8; I++) begin
|
||||
sel2[I] = req_b[I] & ~(|acc2);
|
||||
acc2[I] = req_b[I];
|
||||
oneh_b[id_b[I][3:1]] |= sel2[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// One-hot output also consumed by a downstream parity output.
|
||||
module pri_onehot_shared_consumer (
|
||||
input wire [7:0] req,
|
||||
input wire [7:0][3:0] id,
|
||||
output reg [7:0] oneh,
|
||||
output wire par
|
||||
);
|
||||
always_comb begin
|
||||
reg [7:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 0; I < 8; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][3:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
assign par = ^oneh;
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// Negative / near-miss modules: must NOT be rewritten.
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
// No priority: OR of all decoded fields (output is generally not one-hot).
|
||||
module pri_onehot_orall (
|
||||
input wire [15:0] req,
|
||||
input wire [15:0][4:0] id,
|
||||
output reg [15:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
oneh = '0;
|
||||
for (int I = 0; I < 16; I++)
|
||||
oneh[id[I][4:1]] |= req[I];
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Nonzero default when no request: function is not "0 when all-invalid".
|
||||
module pri_onehot_nonzero_default (
|
||||
input wire [15:0] req,
|
||||
input wire [15:0][4:0] id,
|
||||
output reg [15:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [15:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '1;
|
||||
for (int I = 0; I < 16; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][4:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Non-power-of-two output width.
|
||||
module pri_onehot_nonpow2 (
|
||||
input wire [11:0] req,
|
||||
input wire [11:0][3:0] id,
|
||||
output reg [11:0] oneh
|
||||
);
|
||||
always_comb begin
|
||||
reg [11:0] acc, sel;
|
||||
acc = '0; sel = '0; oneh = '0;
|
||||
for (int I = 0; I < 12; I++) begin
|
||||
sel[I] = req[I] & ~(|acc);
|
||||
acc[I] = req[I];
|
||||
oneh[id[I][3:1]] |= sel[I];
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
// Unrelated mux logic.
|
||||
module pri_onehot_unrelated (
|
||||
input wire [15:0] a,
|
||||
input wire [15:0] b,
|
||||
input wire s,
|
||||
output wire [15:0] y
|
||||
);
|
||||
assign y = s ? a : b;
|
||||
endmodule
|
||||
301
tests/silimate/opt_priority_onehot.ys
Normal file
301
tests/silimate/opt_priority_onehot.ys
Normal file
|
|
@ -0,0 +1,301 @@
|
|||
# Tests for opt_priority_onehot.
|
||||
|
||||
# Helper pattern per positive module: import a gold copy, import a gate copy,
|
||||
# rewrite the gate, assert the rewrite fired, then prove gold == gate by SAT.
|
||||
|
||||
log -header "Basic priority-onehot self-equivalence (N=16, field id[*][4:1])"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_basic
|
||||
proc; opt_clean
|
||||
rename pri_onehot_basic gold
|
||||
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_basic
|
||||
proc; opt_clean
|
||||
select -module pri_onehot_basic
|
||||
opt_priority_onehot
|
||||
select -clear
|
||||
opt_clean
|
||||
select -assert-min 1 w:*prionehot*
|
||||
rename pri_onehot_basic gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "One-based [N:1] ports self-equivalence (regression shape)"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_onebased
|
||||
proc; opt_clean
|
||||
rename pri_onehot_onebased gold
|
||||
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_onebased
|
||||
proc; opt_clean
|
||||
select -module pri_onehot_onebased
|
||||
opt_priority_onehot
|
||||
select -clear
|
||||
opt_clean
|
||||
select -assert-min 1 w:*prionehot*
|
||||
rename pri_onehot_onebased gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Packed field self-equivalence (ID_W == IDX_W, no gap)"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_packed
|
||||
proc; opt_clean
|
||||
rename pri_onehot_packed gold
|
||||
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_packed
|
||||
proc; opt_clean
|
||||
select -module pri_onehot_packed
|
||||
opt_priority_onehot
|
||||
select -clear
|
||||
opt_clean
|
||||
select -assert-min 1 w:*prionehot*
|
||||
rename pri_onehot_packed gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Scaled N=8 self-equivalence"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_w8
|
||||
proc; opt_clean
|
||||
rename pri_onehot_w8 gold
|
||||
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_w8
|
||||
proc; opt_clean
|
||||
select -module pri_onehot_w8
|
||||
opt_priority_onehot
|
||||
select -clear
|
||||
opt_clean
|
||||
select -assert-min 1 w:*prionehot*
|
||||
rename pri_onehot_w8 gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Lane count != output width self-equivalence (N=8, W=16)"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_n8_w16
|
||||
proc; opt_clean
|
||||
rename pri_onehot_n8_w16 gold
|
||||
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_n8_w16
|
||||
proc; opt_clean
|
||||
select -module pri_onehot_n8_w16
|
||||
opt_priority_onehot
|
||||
select -clear
|
||||
opt_clean
|
||||
select -assert-min 1 w:*prionehot*
|
||||
rename pri_onehot_n8_w16 gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "MSB-first priority self-equivalence"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_msb
|
||||
proc; opt_clean
|
||||
rename pri_onehot_msb gold
|
||||
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_msb
|
||||
proc; opt_clean
|
||||
select -module pri_onehot_msb
|
||||
opt_priority_onehot
|
||||
select -clear
|
||||
opt_clean
|
||||
select -assert-min 1 w:*prionehot*
|
||||
rename pri_onehot_msb gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Two independent regions self-equivalence"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_two_regions
|
||||
proc; opt_clean
|
||||
rename pri_onehot_two_regions gold
|
||||
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_two_regions
|
||||
proc; opt_clean
|
||||
select -module pri_onehot_two_regions
|
||||
opt_priority_onehot
|
||||
select -clear
|
||||
opt_clean
|
||||
select -assert-min 2 w:*prionehot*
|
||||
rename pri_onehot_two_regions gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Shared consumer of one-hot output stays equivalent"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_shared_consumer
|
||||
proc; opt_clean
|
||||
rename pri_onehot_shared_consumer gold
|
||||
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_shared_consumer
|
||||
proc; opt_clean
|
||||
select -module pri_onehot_shared_consumer
|
||||
opt_priority_onehot
|
||||
select -clear
|
||||
opt_clean
|
||||
select -assert-min 1 w:*prionehot*
|
||||
rename pri_onehot_shared_consumer gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
sat -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Scaled N=32 structural rewrite"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_w32
|
||||
proc; opt_clean
|
||||
opt_priority_onehot
|
||||
opt_clean
|
||||
select -assert-min 1 w:*prionehot*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative: OR-of-all (no priority) unchanged"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_orall
|
||||
proc; opt_clean
|
||||
opt_priority_onehot
|
||||
select -assert-none w:*prionehot*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative: nonzero all-invalid default unchanged"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_nonzero_default
|
||||
proc; opt_clean
|
||||
opt_priority_onehot
|
||||
select -assert-none w:*prionehot*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative: non-power-of-two output width unchanged"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_nonpow2
|
||||
proc; opt_clean
|
||||
opt_priority_onehot
|
||||
select -assert-none w:*prionehot*
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Negative: unrelated mux logic unchanged"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_unrelated
|
||||
proc; opt_clean
|
||||
select -assert-count 1 t:$mux
|
||||
opt_priority_onehot
|
||||
select -assert-none w:*prionehot*
|
||||
select -assert-count 1 t:$mux
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
log -header "Max-width below lane count leaves design unchanged"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
read -sv opt_priority_onehot.sv
|
||||
verific -import pri_onehot_basic
|
||||
proc; opt_clean
|
||||
opt_priority_onehot -max_width 8
|
||||
select -assert-none w:*prionehot*
|
||||
design -reset
|
||||
log -pop
|
||||
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Add table
Add a link
Reference in a new issue